llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Brandon Wu (4vtomat) <details> <summary>Changes</summary> - [llvm][RISCV] Support Zvfofp8min llvm intrinsics and codegen - fixup! replace undef - [RISCV][clang] Support f8e4m3 and f8e5m2 suffix type for intrinsics --- Patch is 97.29 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/172626.diff 15 Files Affected: - (modified) clang/include/clang/Basic/riscv_vector_common.td (+3) - (modified) clang/include/clang/Support/RISCVVIntrinsicUtils.h (+13-6) - (modified) clang/lib/Sema/SemaRISCV.cpp (+5-1) - (modified) clang/lib/Support/RISCVVIntrinsicUtils.cpp (+56-16) - (modified) clang/utils/TableGen/RISCVVEmitter.cpp (+13-4) - (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+20) - (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp (+3-1) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (+3-1) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td (+127) - (added) llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-alt.ll (+357) - (modified) llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll (+356-4) - (added) llvm/test/CodeGen/RISCV/rvv/vfncvt-sat-f-f-alt.ll (+357) - (added) llvm/test/CodeGen/RISCV/rvv/vfncvt-sat-f-f.ll (+357) - (added) llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-alt.ll (+227) - (modified) llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll (+196-4) ``````````diff diff --git a/clang/include/clang/Basic/riscv_vector_common.td b/clang/include/clang/Basic/riscv_vector_common.td index 7e2d339291713..5cf45fcc845da 100644 --- a/clang/include/clang/Basic/riscv_vector_common.td +++ b/clang/include/clang/Basic/riscv_vector_common.td @@ -181,6 +181,9 @@ class RVVBuiltin<string suffix, string prototype, string type_range, // This builtin has a masked form. bit HasMasked = true; + // This is used by intrinsics that need vtype.altfmt + bit AltFmt = false; + // If HasMasked, this flag states that this builtin has a maskedoff operand. It // is always the first operand in builtin and IR intrinsic. bit HasMaskedOffOperand = true; diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h index 67149f23116e0..4016cc2f77dec 100644 --- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h +++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h @@ -202,7 +202,7 @@ llvm::SmallVector<PrototypeDescriptor> parsePrototypes(llvm::StringRef Prototypes); // Basic type of vector type. -enum class BasicType : uint8_t { +enum class BasicType : uint16_t { Unknown = 0, Int8 = 1 << 0, Int16 = 1 << 1, @@ -212,8 +212,10 @@ enum class BasicType : uint8_t { Float16 = 1 << 5, Float32 = 1 << 6, Float64 = 1 << 7, - MaxOffset = 7, - LLVM_MARK_AS_BITMASK_ENUM(Float64), + F8E4M3 = 1 << 8, + F8E5M2 = 1 << 9, + MaxOffset = 9, + LLVM_MARK_AS_BITMASK_ENUM(F8E5M2), }; // Type of vector type. @@ -228,6 +230,8 @@ enum ScalarTypeKind : uint8_t { UnsignedInteger, Float, BFloat, + FloatE4M3, + FloatE5M2, Invalid, Undefined, }; @@ -412,7 +416,8 @@ class RVVIntrinsic { bool HasBuiltinAlias, llvm::StringRef ManualCodegen, const RVVTypes &Types, const std::vector<int64_t> &IntrinsicTypes, unsigned NF, - Policy PolicyAttrs, bool HasFRMRoundModeOp, unsigned TWiden); + Policy PolicyAttrs, bool HasFRMRoundModeOp, unsigned TWiden, + bool AltFmt); ~RVVIntrinsic() = default; RVVTypePtr getOutputType() const { return OutputType; } @@ -482,7 +487,8 @@ class RVVIntrinsic { static void updateNamesAndPolicy(bool IsMasked, bool HasPolicy, std::string &Name, std::string &BuiltinName, std::string &OverloadedName, - Policy &PolicyAttrs, bool HasFRMRoundModeOp); + Policy &PolicyAttrs, bool HasFRMRoundModeOp, + bool AltFmt); }; // Raw RVV intrinsic info, used to expand later. @@ -517,7 +523,7 @@ struct RVVIntrinsicRecord { uint8_t OverloadedSuffixSize; // Supported type, mask of BasicType. - uint8_t TypeRangeMask; + uint16_t TypeRangeMask; // Supported LMUL. uint8_t Log2LMULMask; @@ -531,6 +537,7 @@ struct RVVIntrinsicRecord { bool HasTailPolicy : 1; bool HasMaskPolicy : 1; bool HasFRMRoundModeOp : 1; + bool AltFmt : 1; bool IsTuple : 1; LLVM_PREFERRED_TYPE(PolicyScheme) uint8_t UnMaskedPolicyScheme : 2; diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp index 6153948a6a589..32d79cab46bde 100644 --- a/clang/lib/Sema/SemaRISCV.cpp +++ b/clang/lib/Sema/SemaRISCV.cpp @@ -137,6 +137,10 @@ static QualType RVVType2Qual(ASTContext &Context, const RVVType *Type) { case ScalarTypeKind::UnsignedInteger: QT = Context.getIntTypeForBitwidth(Type->getElementBitwidth(), false); break; + case ScalarTypeKind::FloatE4M3: + case ScalarTypeKind::FloatE5M2: + QT = Context.getIntTypeForBitwidth(8, false); + break; case ScalarTypeKind::BFloat: QT = Context.BFloat16Ty; break; @@ -379,7 +383,7 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic( RVVIntrinsic::updateNamesAndPolicy(IsMasked, HasPolicy, Name, BuiltinName, OverloadedName, PolicyAttrs, - Record.HasFRMRoundModeOp); + Record.HasFRMRoundModeOp, Record.AltFmt); // Put into IntrinsicList. uint32_t Index = IntrinsicList.size(); diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp b/clang/lib/Support/RISCVVIntrinsicUtils.cpp index 12e209aec92ce..a5430aee6b746 100644 --- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp +++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp @@ -202,6 +202,12 @@ void RVVType::initBuiltinStr() { case ScalarTypeKind::BFloat: BuiltinStr += "y"; break; + case ScalarTypeKind::FloatE4M3: + BuiltinStr += "a"; + break; + case ScalarTypeKind::FloatE5M2: + BuiltinStr += "b"; + break; default: llvm_unreachable("ScalarType is invalid!"); } @@ -244,6 +250,8 @@ void RVVType::initClangBuiltinStr() { ClangBuiltinStr += "int"; break; case ScalarTypeKind::UnsignedInteger: + case ScalarTypeKind::FloatE4M3: + case ScalarTypeKind::FloatE5M2: ClangBuiltinStr += "uint"; break; default: @@ -319,6 +327,8 @@ void RVVType::initTypeStr() { Str += getTypeString("int"); break; case ScalarTypeKind::UnsignedInteger: + case ScalarTypeKind::FloatE4M3: + case ScalarTypeKind::FloatE5M2: Str += getTypeString("uint"); break; default: @@ -346,6 +356,12 @@ void RVVType::initShortStr() { case ScalarTypeKind::UnsignedInteger: ShortStr = "u" + utostr(ElementBitwidth); break; + case ScalarTypeKind::FloatE4M3: + ShortStr = "f8e4m3"; + break; + case ScalarTypeKind::FloatE5M2: + ShortStr = "f8e5m2"; + break; default: llvm_unreachable("Unhandled case!"); } @@ -395,6 +411,14 @@ void RVVType::applyBasicType() { ElementBitwidth = 16; ScalarType = ScalarTypeKind::BFloat; break; + case BasicType::F8E4M3: + ElementBitwidth = 8; + ScalarType = ScalarTypeKind::FloatE4M3; + break; + case BasicType::F8E5M2: + ElementBitwidth = 8; + ScalarType = ScalarTypeKind::FloatE5M2; + break; default: llvm_unreachable("Unhandled type code!"); } @@ -709,11 +733,17 @@ void RVVType::applyModifier(const PrototypeDescriptor &Transformer) { Scale = LMUL.getScale(ElementBitwidth); if (ScalarType == ScalarTypeKind::BFloat) ScalarType = ScalarTypeKind::Float; + if (ScalarType == ScalarTypeKind::FloatE4M3 || + ScalarType == ScalarTypeKind::FloatE5M2) + ScalarType = ScalarTypeKind::BFloat; break; case VectorTypeModifier::Widening4XVector: ElementBitwidth *= 4; LMUL.MulLog2LMUL(2); Scale = LMUL.getScale(ElementBitwidth); + if (ScalarType == ScalarTypeKind::FloatE4M3 || + ScalarType == ScalarTypeKind::FloatE5M2) + ScalarType = ScalarTypeKind::Float; break; case VectorTypeModifier::Widening8XVector: ElementBitwidth *= 8; @@ -938,13 +968,13 @@ RVVTypeCache::computeTypes(BasicType BT, int Log2LMUL, unsigned NF, static uint64_t computeRVVTypeHashValue(BasicType BT, int Log2LMUL, PrototypeDescriptor Proto) { // Layout of hash value: - // 0 8 16 24 32 40 + // 0 8 24 32 40 48 // | Log2LMUL + 3 | BT | Proto.PT | Proto.TM | Proto.VTM | assert(Log2LMUL >= -3 && Log2LMUL <= 3); - return (Log2LMUL + 3) | (static_cast<uint64_t>(BT) & 0xff) << 8 | - ((uint64_t)(Proto.PT & 0xff) << 16) | - ((uint64_t)(Proto.TM & 0xff) << 24) | - ((uint64_t)(Proto.VTM & 0xff) << 32); + return (Log2LMUL + 3) | (static_cast<uint64_t>(BT) & 0xffff) << 8 | + ((uint64_t)(Proto.PT & 0xff) << 24) | + ((uint64_t)(Proto.TM & 0xff) << 32) | + ((uint64_t)(Proto.VTM & 0xff) << 40); } std::optional<RVVTypePtr> RVVTypeCache::computeType(BasicType BT, int Log2LMUL, @@ -974,13 +1004,16 @@ std::optional<RVVTypePtr> RVVTypeCache::computeType(BasicType BT, int Log2LMUL, //===----------------------------------------------------------------------===// // RVVIntrinsic implementation //===----------------------------------------------------------------------===// -RVVIntrinsic::RVVIntrinsic( - StringRef NewName, StringRef Suffix, StringRef NewOverloadedName, - StringRef OverloadedSuffix, StringRef IRName, bool IsMasked, - bool HasMaskedOffOperand, bool HasVL, PolicyScheme Scheme, - bool SupportOverloading, bool HasBuiltinAlias, StringRef ManualCodegen, - const RVVTypes &OutInTypes, const std::vector<int64_t> &NewIntrinsicTypes, - unsigned NF, Policy NewPolicyAttrs, bool HasFRMRoundModeOp, unsigned TWiden) +RVVIntrinsic::RVVIntrinsic(StringRef NewName, StringRef Suffix, + StringRef NewOverloadedName, + StringRef OverloadedSuffix, StringRef IRName, + bool IsMasked, bool HasMaskedOffOperand, bool HasVL, + PolicyScheme Scheme, bool SupportOverloading, + bool HasBuiltinAlias, StringRef ManualCodegen, + const RVVTypes &OutInTypes, + const std::vector<int64_t> &NewIntrinsicTypes, + unsigned NF, Policy NewPolicyAttrs, + bool HasFRMRoundModeOp, unsigned TWiden, bool AltFmt) : IRName(IRName), IsMasked(IsMasked), HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL), Scheme(Scheme), SupportOverloading(SupportOverloading), HasBuiltinAlias(HasBuiltinAlias), @@ -1000,7 +1033,7 @@ RVVIntrinsic::RVVIntrinsic( OverloadedName += "_" + OverloadedSuffix.str(); updateNamesAndPolicy(IsMasked, hasPolicy(), Name, BuiltinName, OverloadedName, - PolicyAttrs, HasFRMRoundModeOp); + PolicyAttrs, HasFRMRoundModeOp, AltFmt); // Init OutputType and InputTypes OutputType = OutInTypes[0]; @@ -1141,9 +1174,12 @@ RVVIntrinsic::getSupportedMaskedPolicies(bool HasTailPolicy, "and mask policy"); } -void RVVIntrinsic::updateNamesAndPolicy( - bool IsMasked, bool HasPolicy, std::string &Name, std::string &BuiltinName, - std::string &OverloadedName, Policy &PolicyAttrs, bool HasFRMRoundModeOp) { +void RVVIntrinsic::updateNamesAndPolicy(bool IsMasked, bool HasPolicy, + std::string &Name, + std::string &BuiltinName, + std::string &OverloadedName, + Policy &PolicyAttrs, + bool HasFRMRoundModeOp, bool AltFmt) { auto appendPolicySuffix = [&](const std::string &suffix) { Name += suffix; @@ -1156,6 +1192,9 @@ void RVVIntrinsic::updateNamesAndPolicy( BuiltinName += "_rm"; } + if (AltFmt) + BuiltinName += "_alt"; + if (IsMasked) { if (PolicyAttrs.isTUMUPolicy()) appendPolicySuffix("_tumu"); @@ -1239,6 +1278,7 @@ raw_ostream &operator<<(raw_ostream &OS, const RVVIntrinsicRecord &Record) { OS << "/*HasTailPolicy=*/" << (int)Record.HasTailPolicy << ", "; OS << "/*HasMaskPolicy=*/" << (int)Record.HasMaskPolicy << ", "; OS << "/*HasFRMRoundModeOp=*/" << (int)Record.HasFRMRoundModeOp << ", "; + OS << "/*AltFmt=*/" << (int)Record.AltFmt << ","; OS << "/*IsTuple=*/" << (int)Record.IsTuple << ", "; OS << "/*UnMaskedPolicyScheme=*/" << (PolicyScheme)Record.UnMaskedPolicyScheme << ", "; diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp index c316dfd30d9bf..970132d85d5b6 100644 --- a/clang/utils/TableGen/RISCVVEmitter.cpp +++ b/clang/utils/TableGen/RISCVVEmitter.cpp @@ -65,6 +65,7 @@ struct SemaRecord { bool HasTailPolicy : 1; bool HasMaskPolicy : 1; bool HasFRMRoundModeOp : 1; + bool AltFmt : 1; bool IsTuple : 1; LLVM_PREFERRED_TYPE(PolicyScheme) uint8_t UnMaskedPolicyScheme : 2; @@ -147,6 +148,10 @@ static BasicType ParseBasicType(char c) { return BasicType::Float64; case 'y': return BasicType::BFloat16; + case 'a': + return BasicType::F8E4M3; + case 'b': + return BasicType::F8E5M2; default: return BasicType::Unknown; } @@ -641,6 +646,7 @@ void RVVEmitter::createRVVIntrinsics( std::vector<int64_t> Log2LMULList = R->getValueAsListOfInts("Log2LMUL"); bool HasTailPolicy = R->getValueAsBit("HasTailPolicy"); bool HasMaskPolicy = R->getValueAsBit("HasMaskPolicy"); + bool AltFmt = R->getValueAsBit("AltFmt"); bool SupportOverloading = R->getValueAsBit("SupportOverloading"); bool HasBuiltinAlias = R->getValueAsBit("HasBuiltinAlias"); StringRef ManualCodegen = R->getValueAsString("ManualCodegen"); @@ -701,7 +707,7 @@ void RVVEmitter::createRVVIntrinsics( /*IsMasked=*/false, /*HasMaskedOffOperand=*/false, HasVL, UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias, ManualCodegen, *Types, IntrinsicTypes, NF, DefaultPolicy, - HasFRMRoundModeOp, TWiden)); + HasFRMRoundModeOp, TWiden, AltFmt)); if (UnMaskedPolicyScheme != PolicyScheme::SchemeNone) for (auto P : SupportedUnMaskedPolicies) { SmallVector<PrototypeDescriptor> PolicyPrototype = @@ -716,7 +722,7 @@ void RVVEmitter::createRVVIntrinsics( /*IsMask=*/false, /*HasMaskedOffOperand=*/false, HasVL, UnMaskedPolicyScheme, SupportOverloading, HasBuiltinAlias, ManualCodegen, *PolicyTypes, IntrinsicTypes, NF, P, - HasFRMRoundModeOp, TWiden)); + HasFRMRoundModeOp, TWiden, AltFmt)); } if (!HasMasked) continue; @@ -727,7 +733,8 @@ void RVVEmitter::createRVVIntrinsics( Name, SuffixStr, OverloadedName, OverloadedSuffixStr, MaskedIRName, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme, SupportOverloading, HasBuiltinAlias, ManualCodegen, *MaskTypes, - IntrinsicTypes, NF, DefaultPolicy, HasFRMRoundModeOp, TWiden)); + IntrinsicTypes, NF, DefaultPolicy, HasFRMRoundModeOp, TWiden, + AltFmt)); if (MaskedPolicyScheme == PolicyScheme::SchemeNone) continue; for (auto P : SupportedMaskedPolicies) { @@ -742,7 +749,7 @@ void RVVEmitter::createRVVIntrinsics( MaskedIRName, /*IsMasked=*/true, HasMaskedOffOperand, HasVL, MaskedPolicyScheme, SupportOverloading, HasBuiltinAlias, ManualCodegen, *PolicyTypes, IntrinsicTypes, NF, P, - HasFRMRoundModeOp, TWiden)); + HasFRMRoundModeOp, TWiden, AltFmt)); } } // End for Log2LMULList } // End for TypeRange @@ -780,6 +787,7 @@ void RVVEmitter::createRVVIntrinsics( SR.HasMaskedOffOperand = HasMaskedOffOperand; SR.HasTailPolicy = HasTailPolicy; SR.HasMaskPolicy = HasMaskPolicy; + SR.AltFmt = AltFmt; SR.UnMaskedPolicyScheme = static_cast<uint8_t>(UnMaskedPolicyScheme); SR.MaskedPolicyScheme = static_cast<uint8_t>(MaskedPolicyScheme); SR.Prototype = std::move(BasicPrototype); @@ -824,6 +832,7 @@ void RVVEmitter::createRVVIntrinsicRecords(std::vector<RVVIntrinsicRecord> &Out, R.HasMaskedOffOperand = SR.HasMaskedOffOperand; R.HasTailPolicy = SR.HasTailPolicy; R.HasMaskPolicy = SR.HasMaskPolicy; + R.AltFmt = SR.AltFmt; R.UnMaskedPolicyScheme = SR.UnMaskedPolicyScheme; R.MaskedPolicyScheme = SR.MaskedPolicyScheme; R.IsTuple = SR.IsTuple; diff --git a/llvm/include/llvm/IR/IntrinsicsRISCV.td b/llvm/include/llvm/IR/IntrinsicsRISCV.td index 77fcc46ea5a89..9088e5e6a357b 100644 --- a/llvm/include/llvm/IR/IntrinsicsRISCV.td +++ b/llvm/include/llvm/IR/IntrinsicsRISCV.td @@ -1958,6 +1958,26 @@ let TargetPrefix = "riscv" in { let TargetPrefix = "riscv" in def int_riscv_pause : DefaultAttrsIntrinsic<[], [], [IntrNoMem, IntrHasSideEffects]>; + +//===----------------------------------------------------------------------===// +// Zvfofp8min - OFP8 conversion extension +// The Zvfofp8min extension provides basic support for the two 8-bit +// floating-point formats defined in the Open Compute Project OFP8 +// specification, OFP8 E4M3 and OFP8 E5M2. +let TargetPrefix = "riscv" in { + // OFP8 to BF16 conversion instructions + defm vfwcvt_f_f_v_alt : RISCVConversion; + // BF16 to OFP8 conversion instructions + defm vfncvt_sat_f_f_w : RISCVConversionRoundingMode; + defm vfncvt_f_f_w_alt : RISCVConversionRoundingMode; + defm vfncvt_sat_f_f_w_alt : RISCVConversionRoundingMode; + // FP32 to OFP8 conversion instructions + defm vfncvt_f_f_q : RISCVConversionRoundingMode; + defm vfncvt_f_f_q_alt : RISCVConversionRoundingMode; + defm vfncvt_sat_f_f_q : RISCVConversionRoundingMode; + defm vfncvt_sat_f_f_q_alt : RISCVConversionRoundingMode; +} // TargetPrefix = "riscv" + // Vendor extensions //===----------------------------------------------------------------------===// include "llvm/IR/IntrinsicsRISCVXTHead.td" diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp index 7b9c4b3e800cd..f2c5f6947aa00 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp @@ -216,11 +216,13 @@ void RISCVInstPrinter::printVTypeI(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O) { unsigned Imm = MI->getOperand(OpNo).getImm(); // Print the raw immediate for reserved values: vlmul[2:0]=4, vsew[2:0]=0b1xx, - // altfmt=1 without zvfbfa extension, or non-zero in bits 9 and above. + // altfmt=1 without zvfbfa or zvfofp8min extension, or non-zero in bits 9 and + // above. if (RISCVVType::getVLMUL(Imm) == RISCVVType::VLMUL::LMUL_RESERVED || RISCVVType::getSEW(Imm) > 64 || (RISCVVType::isAltFmt(Imm) && !(STI.hasFeature(RISCV::FeatureStdExtZvfbfa) || + STI.hasFeature(RISCV::FeatureStdExtZvfofp8min) || STI.hasFeature(RISCV::FeatureVendorXSfvfbfexp16e))) || (Imm >> 9) != 0) { O << formatImm(Imm); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index e07d7b5ee5563..a32f6a566493f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -5851,8 +5851,9 @@ multiclass VPatConversionWF_VI<string intrinsic, string instruction, } multiclass VPatConversionWF_VF<string intrinsic, string instruction, + list<VTypeInfoToWide> wlist = AllWidenableFloatVectors, bit isSEWAware = 0> { - foreach fvtiToFWti = AllWidenableFloatVectors in { + foreach fvtiToFWti = wlist in { defvar fvti = fvtiToFWti.Vti; defvar fwti = fvtiToFWti.Wti; // Define vfwcvt.f.f.v for f16 when Zvfhmin is enable. @@ -7177,6 +7178,7 @@ defm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_xu_v", "PseudoVFWCVT_F_XU", defm : VPatConversionWF_VI<"int_riscv_vfwcvt_f_x_v", "PseudoVFWCVT_F_X", isSEWAware=1>; defm : VPatConversionWF_VF<"int_riscv_vfwcvt_f_f_v", "PseudoVFWCVT_F_F", + wlist=AllWidenableFloatVectors, isSEWAware=1>; //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td index 86cab697cbf55..b067488ea662f 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td @@ -24,3 +24,130 @@ let Predicates = [HasStdExtZvfofp8min], Constraints = "@earlyclobber $vd", defm VFNCVT_F_F_Q : VNCVTF_FV_VS2<"vfncvt.f.f.q", 0b010010, 0b11001>; defm VFNCVT_SAT_F_F_Q : VNCVTF_FV_VS2<"vfncvt.sat.f.f.q", 0b010010, 0b11011>; } + +//===----------------------------------------------------------------------===// +// Pseudo instructions +//===----------------------------------------------------------------------===// +defvar MxListQ = [V_MF8, V_MF4, V_MF2, V_M1, V_M2]; + +defset list<VTypeInfoToWide> AllWidenableIntToBFloatVectors = { + def : VTypeInfoToWide<VI8MF8, VBF16MF4>; + def : VTypeInfoToWide<VI8MF4, VBF16MF2>; + def : VTypeInfoToWide<VI8MF2, VBF16M1>; + def : VTypeInfoToWide<VI8M1, VBF16M2>; + ... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/172626 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
