llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-risc-v Author: Brandon Wu (4vtomat) <details> <summary>Changes</summary> intrinsic spec: https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/417 stack on: https://github.com/llvm/llvm-project/pull/172626 --- Patch is 1.03 MiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/172630.diff 28 Files Affected: - (modified) clang/include/clang/Basic/riscv_vector.td (+88) - (modified) clang/include/clang/Basic/riscv_vector_common.td (+3) - (modified) clang/include/clang/Support/RISCVVIntrinsicUtils.h (+13-6) - (modified) clang/lib/Sema/SemaRISCV.cpp (+5-1) - (modified) clang/lib/Support/RISCVVIntrinsicUtils.cpp (+56-16) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/vfncvt.c (+848) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/vfncvtbf16.c (+1108) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/vfwcvtbf16.c (+264) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/vfncvt.c (+848) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/vfncvtbf16.c (+1080) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/overloaded/vfwcvtbf16.c (+264) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/vfncvt.c (+1836) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/vfncvtbf16.c (+2478) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/non-overloaded/vfwcvtbf16.c (+602) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/vfncvt.c (+1790) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/vfncvtbf16.c (+2394) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/policy/overloaded/vfwcvtbf16.c (+602) - (modified) clang/utils/TableGen/RISCVVEmitter.cpp (+13-4) - (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+20) - (modified) llvm/lib/Target/RISCV/MCTargetDesc/RISCVInstPrinter.cpp (+3-1) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td (+3-1) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfoZvfofp8min.td (+127) - (added) llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f-alt.ll (+357) - (modified) llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll (+356-4) - (added) llvm/test/CodeGen/RISCV/rvv/vfncvt-sat-f-f-alt.ll (+357) - (added) llvm/test/CodeGen/RISCV/rvv/vfncvt-sat-f-f.ll (+357) - (added) llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f-alt.ll (+227) - (modified) llvm/test/CodeGen/RISCV/rvv/vfwcvt-f-f.ll (+196-4) ``````````diff diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index b45f863803968..c899dc70fc0b7 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -1356,6 +1356,19 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { let RequiredFeatures = ["zvfbfmin"], Log2LMUL = [-2, -1, 0, 1, 2] in def vfwcvtbf16_f_f_v : RVVConvBuiltin<"Fw", "Fwv", "y", "vfwcvtbf16_f">; +// Zvfofp8min +let Log2LMUL = [-3, -2, -1, 0, 1, 2], + RequiredFeatures = ["zvfofp8min"], + UnMaskedPolicyScheme = HasPassthruOperand in { + let OverloadedName = "vfwcvt_f_f8e4m3_bf16" in + defm : RVVConvBuiltinSet<"vfwcvt_f_f_v", "a", [["vw", "wv"]]>; + let OverloadedName = "vfwcvt_f_f8e5m2_bf16", + IRName = "vfwcvt_f_f_v_alt", + MaskedIRName = "vfwcvt_f_f_v_alt_mask", + AltFmt = 1 in + defm : RVVConvBuiltinSet<"vfwcvt_f_f_v", "b", [["vw", "wv"]]>; +} + let ManualCodegen = [{ { return emitRVVFloatingConvBuiltin(this, E, ReturnValue, ResultType, ID, @@ -1434,6 +1447,42 @@ let ManualCodegen = [{ Log2LMUL = [-2, -1, 0, 1, 2], OverloadedName = "vfncvtbf16_f" in defm : RVVConvBuiltinSet<"vfncvtbf16_f_f_w", "y", [["v", "vFwu"]]>; + + // Zvfofp8min + let RequiredFeatures = ["zvfofp8min"] in { + let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { + let OverloadedName = "vfncvt_f_bf16_f8e4m3" in + defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "a", [["wv", "vwu"]]>; + let OverloadedName = "vfncvt_f_bf16_f8e5m2", + IRName = "vfncvt_f_f_w_alt", + MaskedIRName = "vfncvt_f_f_w_alt_mask", + AltFmt = 1 in + defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "b", [["wv", "vwu"]]>; + let OverloadedName = "vfncvt_sat_f_bf16_f8e4m3" in + defm : RVVConvBuiltinSet<"vfncvt_sat_f_f_w", "a", [["wv", "vwu"]]>; + let OverloadedName = "vfncvt_sat_f_bf16_f8e5m2", + IRName = "vfncvt_sat_f_f_w_alt", + MaskedIRName = "vfncvt_sat_f_f_w_alt_mask", + AltFmt = 1 in + defm : RVVConvBuiltinSet<"vfncvt_sat_f_f_w", "b", [["wv", "vwu"]]>; + } + let Log2LMUL = [-3, -2, -1, 0, 1] in { + let OverloadedName = "vfncvt_f_f8e4m3" in + defm : RVVConvBuiltinSet<"vfncvt_f_f_q", "a", [["v", "vqu"]]>; + let OverloadedName = "vfncvt_f_f8e5m2", + IRName = "vfncvt_f_f_q_alt", + MaskedIRName = "vfncvt_f_f_q_alt_mask", + AltFmt = 1 in + defm : RVVConvBuiltinSet<"vfncvt_f_f_q", "b", [["v", "vqu"]]>; + let OverloadedName = "vfncvt_sat_f_f8e4m3" in + defm : RVVConvBuiltinSet<"vfncvt_sat_f_f_q", "a", [["v", "vqu"]]>; + let OverloadedName = "vfncvt_sat_f_f8e5m2", + IRName = "vfncvt_sat_f_f_q_alt", + MaskedIRName = "vfncvt_sat_f_f_q_alt_mask", + AltFmt = 1 in + defm : RVVConvBuiltinSet<"vfncvt_sat_f_f_q", "b", [["v", "vqu"]]>; + } + } } // 13.17. Single-Width Floating-Point/Integer Type-Convert Instructions @@ -1506,6 +1555,45 @@ let ManualCodegen = [{ let Log2LMUL = [-2, -1, 0, 1, 2], OverloadedName = "vfncvtbf16_f" in defm : RVVConvBuiltinSet<"vfncvtbf16_f_f_w", "y", [["v", "vFw"]]>; + + // Zvfofp8min + let RequiredFeatures = ["zvfofp8min"] in { + let Log2LMUL = [-3, -2, -1, 0, 1, 2] in { + let OverloadedName = "vfncvt_f_bf16_f8e4m3" in + defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "a", [["wv", "vw"]]>; + let OverloadedName = "vfncvt_f_bf16_f8e5m2", + IRName = "vfncvt_f_f_w_alt", + MaskedIRName = "vfncvt_f_f_w_alt_mask", + AltFmt = 1 in + defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "b", [["wv", "vw"]]>; + let OverloadedName = "vfncvt_sat_f_bf16_f8e4m3" in + defm : RVVConvBuiltinSet<"vfncvt_sat_f_f_w", "a", [["wv", "vw"]]>; + let OverloadedName = "vfncvt_sat_f_bf16_f8e5m2", + IRName = "vfncvt_sat_f_f_w_alt", + MaskedIRName = "vfncvt_sat_f_f_w_alt_mask", + AltFmt = 1 in + defm : RVVConvBuiltinSet<"vfncvt_sat_f_f_w", "b", [["wv", "vw"]]>; + } + let Log2LMUL = [-3, -2, -1, 0, 1] in { + // The non-policy overloaded version will have conflict with zvfhmin, so we + // need another naming. The reason policy version doesn't have this issue is + // because of passthru operand which is f16 in zvfhmin and u8 in this case. + let OverloadedName = "vfncvt_f_f8e4m3" in + defm : RVVConvBuiltinSet<"vfncvt_f_f_q", "a", [["v", "vq"]]>; + let OverloadedName = "vfncvt_f_f8e5m2", + IRName = "vfncvt_f_f_q_alt", + MaskedIRName = "vfncvt_f_f_q_alt_mask", + AltFmt = 1 in + defm : RVVConvBuiltinSet<"vfncvt_f_f_q", "b", [["v", "vq"]]>; + let OverloadedName = "vfncvt_sat_f_f8e4m3" in + defm : RVVConvBuiltinSet<"vfncvt_sat_f_f_q", "a", [["v", "vq"]]>; + let OverloadedName = "vfncvt_sat_f_f8e5m2", + IRName = "vfncvt_sat_f_f_q_alt", + MaskedIRName = "vfncvt_sat_f_f_q_alt_mask", + AltFmt = 1 in + defm : RVVConvBuiltinSet<"vfncvt_sat_f_f_q", "b", [["v", "vq"]]>; + } + } } } diff --git a/clang/include/clang/Basic/riscv_vector_common.td b/clang/include/clang/Basic/riscv_vector_common.td index 7e2d339291713..5cf45fcc845da 100644 --- a/clang/include/clang/Basic/riscv_vector_common.td +++ b/clang/include/clang/Basic/riscv_vector_common.td @@ -181,6 +181,9 @@ class RVVBuiltin<string suffix, string prototype, string type_range, // This builtin has a masked form. bit HasMasked = true; + // This is used by intrinsics that need vtype.altfmt + bit AltFmt = false; + // If HasMasked, this flag states that this builtin has a maskedoff operand. It // is always the first operand in builtin and IR intrinsic. bit HasMaskedOffOperand = true; diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h index 67149f23116e0..4016cc2f77dec 100644 --- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h +++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h @@ -202,7 +202,7 @@ llvm::SmallVector<PrototypeDescriptor> parsePrototypes(llvm::StringRef Prototypes); // Basic type of vector type. -enum class BasicType : uint8_t { +enum class BasicType : uint16_t { Unknown = 0, Int8 = 1 << 0, Int16 = 1 << 1, @@ -212,8 +212,10 @@ enum class BasicType : uint8_t { Float16 = 1 << 5, Float32 = 1 << 6, Float64 = 1 << 7, - MaxOffset = 7, - LLVM_MARK_AS_BITMASK_ENUM(Float64), + F8E4M3 = 1 << 8, + F8E5M2 = 1 << 9, + MaxOffset = 9, + LLVM_MARK_AS_BITMASK_ENUM(F8E5M2), }; // Type of vector type. @@ -228,6 +230,8 @@ enum ScalarTypeKind : uint8_t { UnsignedInteger, Float, BFloat, + FloatE4M3, + FloatE5M2, Invalid, Undefined, }; @@ -412,7 +416,8 @@ class RVVIntrinsic { bool HasBuiltinAlias, llvm::StringRef ManualCodegen, const RVVTypes &Types, const std::vector<int64_t> &IntrinsicTypes, unsigned NF, - Policy PolicyAttrs, bool HasFRMRoundModeOp, unsigned TWiden); + Policy PolicyAttrs, bool HasFRMRoundModeOp, unsigned TWiden, + bool AltFmt); ~RVVIntrinsic() = default; RVVTypePtr getOutputType() const { return OutputType; } @@ -482,7 +487,8 @@ class RVVIntrinsic { static void updateNamesAndPolicy(bool IsMasked, bool HasPolicy, std::string &Name, std::string &BuiltinName, std::string &OverloadedName, - Policy &PolicyAttrs, bool HasFRMRoundModeOp); + Policy &PolicyAttrs, bool HasFRMRoundModeOp, + bool AltFmt); }; // Raw RVV intrinsic info, used to expand later. @@ -517,7 +523,7 @@ struct RVVIntrinsicRecord { uint8_t OverloadedSuffixSize; // Supported type, mask of BasicType. - uint8_t TypeRangeMask; + uint16_t TypeRangeMask; // Supported LMUL. uint8_t Log2LMULMask; @@ -531,6 +537,7 @@ struct RVVIntrinsicRecord { bool HasTailPolicy : 1; bool HasMaskPolicy : 1; bool HasFRMRoundModeOp : 1; + bool AltFmt : 1; bool IsTuple : 1; LLVM_PREFERRED_TYPE(PolicyScheme) uint8_t UnMaskedPolicyScheme : 2; diff --git a/clang/lib/Sema/SemaRISCV.cpp b/clang/lib/Sema/SemaRISCV.cpp index 6153948a6a589..32d79cab46bde 100644 --- a/clang/lib/Sema/SemaRISCV.cpp +++ b/clang/lib/Sema/SemaRISCV.cpp @@ -137,6 +137,10 @@ static QualType RVVType2Qual(ASTContext &Context, const RVVType *Type) { case ScalarTypeKind::UnsignedInteger: QT = Context.getIntTypeForBitwidth(Type->getElementBitwidth(), false); break; + case ScalarTypeKind::FloatE4M3: + case ScalarTypeKind::FloatE5M2: + QT = Context.getIntTypeForBitwidth(8, false); + break; case ScalarTypeKind::BFloat: QT = Context.BFloat16Ty; break; @@ -379,7 +383,7 @@ void RISCVIntrinsicManagerImpl::InitRVVIntrinsic( RVVIntrinsic::updateNamesAndPolicy(IsMasked, HasPolicy, Name, BuiltinName, OverloadedName, PolicyAttrs, - Record.HasFRMRoundModeOp); + Record.HasFRMRoundModeOp, Record.AltFmt); // Put into IntrinsicList. uint32_t Index = IntrinsicList.size(); diff --git a/clang/lib/Support/RISCVVIntrinsicUtils.cpp b/clang/lib/Support/RISCVVIntrinsicUtils.cpp index 12e209aec92ce..a5430aee6b746 100644 --- a/clang/lib/Support/RISCVVIntrinsicUtils.cpp +++ b/clang/lib/Support/RISCVVIntrinsicUtils.cpp @@ -202,6 +202,12 @@ void RVVType::initBuiltinStr() { case ScalarTypeKind::BFloat: BuiltinStr += "y"; break; + case ScalarTypeKind::FloatE4M3: + BuiltinStr += "a"; + break; + case ScalarTypeKind::FloatE5M2: + BuiltinStr += "b"; + break; default: llvm_unreachable("ScalarType is invalid!"); } @@ -244,6 +250,8 @@ void RVVType::initClangBuiltinStr() { ClangBuiltinStr += "int"; break; case ScalarTypeKind::UnsignedInteger: + case ScalarTypeKind::FloatE4M3: + case ScalarTypeKind::FloatE5M2: ClangBuiltinStr += "uint"; break; default: @@ -319,6 +327,8 @@ void RVVType::initTypeStr() { Str += getTypeString("int"); break; case ScalarTypeKind::UnsignedInteger: + case ScalarTypeKind::FloatE4M3: + case ScalarTypeKind::FloatE5M2: Str += getTypeString("uint"); break; default: @@ -346,6 +356,12 @@ void RVVType::initShortStr() { case ScalarTypeKind::UnsignedInteger: ShortStr = "u" + utostr(ElementBitwidth); break; + case ScalarTypeKind::FloatE4M3: + ShortStr = "f8e4m3"; + break; + case ScalarTypeKind::FloatE5M2: + ShortStr = "f8e5m2"; + break; default: llvm_unreachable("Unhandled case!"); } @@ -395,6 +411,14 @@ void RVVType::applyBasicType() { ElementBitwidth = 16; ScalarType = ScalarTypeKind::BFloat; break; + case BasicType::F8E4M3: + ElementBitwidth = 8; + ScalarType = ScalarTypeKind::FloatE4M3; + break; + case BasicType::F8E5M2: + ElementBitwidth = 8; + ScalarType = ScalarTypeKind::FloatE5M2; + break; default: llvm_unreachable("Unhandled type code!"); } @@ -709,11 +733,17 @@ void RVVType::applyModifier(const PrototypeDescriptor &Transformer) { Scale = LMUL.getScale(ElementBitwidth); if (ScalarType == ScalarTypeKind::BFloat) ScalarType = ScalarTypeKind::Float; + if (ScalarType == ScalarTypeKind::FloatE4M3 || + ScalarType == ScalarTypeKind::FloatE5M2) + ScalarType = ScalarTypeKind::BFloat; break; case VectorTypeModifier::Widening4XVector: ElementBitwidth *= 4; LMUL.MulLog2LMUL(2); Scale = LMUL.getScale(ElementBitwidth); + if (ScalarType == ScalarTypeKind::FloatE4M3 || + ScalarType == ScalarTypeKind::FloatE5M2) + ScalarType = ScalarTypeKind::Float; break; case VectorTypeModifier::Widening8XVector: ElementBitwidth *= 8; @@ -938,13 +968,13 @@ RVVTypeCache::computeTypes(BasicType BT, int Log2LMUL, unsigned NF, static uint64_t computeRVVTypeHashValue(BasicType BT, int Log2LMUL, PrototypeDescriptor Proto) { // Layout of hash value: - // 0 8 16 24 32 40 + // 0 8 24 32 40 48 // | Log2LMUL + 3 | BT | Proto.PT | Proto.TM | Proto.VTM | assert(Log2LMUL >= -3 && Log2LMUL <= 3); - return (Log2LMUL + 3) | (static_cast<uint64_t>(BT) & 0xff) << 8 | - ((uint64_t)(Proto.PT & 0xff) << 16) | - ((uint64_t)(Proto.TM & 0xff) << 24) | - ((uint64_t)(Proto.VTM & 0xff) << 32); + return (Log2LMUL + 3) | (static_cast<uint64_t>(BT) & 0xffff) << 8 | + ((uint64_t)(Proto.PT & 0xff) << 24) | + ((uint64_t)(Proto.TM & 0xff) << 32) | + ((uint64_t)(Proto.VTM & 0xff) << 40); } std::optional<RVVTypePtr> RVVTypeCache::computeType(BasicType BT, int Log2LMUL, @@ -974,13 +1004,16 @@ std::optional<RVVTypePtr> RVVTypeCache::computeType(BasicType BT, int Log2LMUL, //===----------------------------------------------------------------------===// // RVVIntrinsic implementation //===----------------------------------------------------------------------===// -RVVIntrinsic::RVVIntrinsic( - StringRef NewName, StringRef Suffix, StringRef NewOverloadedName, - StringRef OverloadedSuffix, StringRef IRName, bool IsMasked, - bool HasMaskedOffOperand, bool HasVL, PolicyScheme Scheme, - bool SupportOverloading, bool HasBuiltinAlias, StringRef ManualCodegen, - const RVVTypes &OutInTypes, const std::vector<int64_t> &NewIntrinsicTypes, - unsigned NF, Policy NewPolicyAttrs, bool HasFRMRoundModeOp, unsigned TWiden) +RVVIntrinsic::RVVIntrinsic(StringRef NewName, StringRef Suffix, + StringRef NewOverloadedName, + StringRef OverloadedSuffix, StringRef IRName, + bool IsMasked, bool HasMaskedOffOperand, bool HasVL, + PolicyScheme Scheme, bool SupportOverloading, + bool HasBuiltinAlias, StringRef ManualCodegen, + const RVVTypes &OutInTypes, + const std::vector<int64_t> &NewIntrinsicTypes, + unsigned NF, Policy NewPolicyAttrs, + bool HasFRMRoundModeOp, unsigned TWiden, bool AltFmt) : IRName(IRName), IsMasked(IsMasked), HasMaskedOffOperand(HasMaskedOffOperand), HasVL(HasVL), Scheme(Scheme), SupportOverloading(SupportOverloading), HasBuiltinAlias(HasBuiltinAlias), @@ -1000,7 +1033,7 @@ RVVIntrinsic::RVVIntrinsic( OverloadedName += "_" + OverloadedSuffix.str(); updateNamesAndPolicy(IsMasked, hasPolicy(), Name, BuiltinName, OverloadedName, - PolicyAttrs, HasFRMRoundModeOp); + PolicyAttrs, HasFRMRoundModeOp, AltFmt); // Init OutputType and InputTypes OutputType = OutInTypes[0]; @@ -1141,9 +1174,12 @@ RVVIntrinsic::getSupportedMaskedPolicies(bool HasTailPolicy, "and mask policy"); } -void RVVIntrinsic::updateNamesAndPolicy( - bool IsMasked, bool HasPolicy, std::string &Name, std::string &BuiltinName, - std::string &OverloadedName, Policy &PolicyAttrs, bool HasFRMRoundModeOp) { +void RVVIntrinsic::updateNamesAndPolicy(bool IsMasked, bool HasPolicy, + std::string &Name, + std::string &BuiltinName, + std::string &OverloadedName, + Policy &PolicyAttrs, + bool HasFRMRoundModeOp, bool AltFmt) { auto appendPolicySuffix = [&](const std::string &suffix) { Name += suffix; @@ -1156,6 +1192,9 @@ void RVVIntrinsic::updateNamesAndPolicy( BuiltinName += "_rm"; } + if (AltFmt) + BuiltinName += "_alt"; + if (IsMasked) { if (PolicyAttrs.isTUMUPolicy()) appendPolicySuffix("_tumu"); @@ -1239,6 +1278,7 @@ raw_ostream &operator<<(raw_ostream &OS, const RVVIntrinsicRecord &Record) { OS << "/*HasTailPolicy=*/" << (int)Record.HasTailPolicy << ", "; OS << "/*HasMaskPolicy=*/" << (int)Record.HasMaskPolicy << ", "; OS << "/*HasFRMRoundModeOp=*/" << (int)Record.HasFRMRoundModeOp << ", "; + OS << "/*AltFmt=*/" << (int)Record.AltFmt << ","; OS << "/*IsTuple=*/" << (int)Record.IsTuple << ", "; OS << "/*UnMaskedPolicyScheme=*/" << (PolicyScheme)Record.UnMaskedPolicyScheme << ", "; diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/vfncvt.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/vfncvt.c new file mode 100644 index 0000000000000..3daae3806afdf --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-sifive/non-policy/non-overloaded/vfncvt.c @@ -0,0 +1,848 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zvfbfmin \ +// RUN: -target-feature +experimental-zvfofp8min -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include <riscv_vector.h> + +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_f_f_q_f8e4m3mf8( +// CHECK-RV64-SAME: <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: [[ENTRY:.*:]] +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] +// +vuint8mf8_t test_vfncvt_f_f_q_f8e4m3mf8(vfloat32mf2_t vs2, size_t vl) { + return __riscv_vfncvt_f_f_q_f8e4m3mf8(vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf8( +// CHECK-RV64-SAME: <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: [[ENTRY:.*:]] +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv1i8.nxv1f32.i64(<vscale x 1 x i8> poison, <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i8> [[TMP0]] +// +vuint8mf8_t test_vfncvt_sat_f_f_q_f8e4m3mf8(vfloat32mf2_t vs2, size_t vl) { + return __riscv_vfncvt_sat_f_f_q_f8e4m3mf8(vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_f_f_q_f8e4m3mf4( +// CHECK-RV64-SAME: <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: [[ENTRY:.*:]] +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] +// +vuint8mf4_t test_vfncvt_f_f_q_f8e4m3mf4(vfloat32m1_t vs2, size_t vl) { + return __riscv_vfncvt_f_f_q_f8e4m3mf4(vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i8> @test_vfncvt_sat_f_f_q_f8e4m3mf4( +// CHECK-RV64-SAME: <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: [[ENTRY:.*:]] +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i8> @llvm.riscv.vfncvt.sat.f.f.q.nxv2i8.nxv2f32.i64(<vscale x 2 x i8> poison, <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i8> [[TMP0]] +// +vuint8mf4_t test_vfncvt_sat_f_f_q_f8e4m3mf4(vfloat32m1_t vs2, size_t vl) { + return __riscv_vfncvt_sat_f_f_q_f8e4m3mf4(vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> @test_vfncvt_f_f_q_f8e4m3mf2( +// CHECK-RV64-SAME: <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: [[ENTRY:.*:]] +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i8> @llvm.riscv.vfncvt.f.f.q.nxv4i8.nxv4f32.i64(<vscale x 4 x i8> poison, <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i8> [[TMP0]] +// +vuint8mf2_t test_vfncvt_f_f_q_f8e4m3mf2(vfloat32m2_t vs2, size_t vl) { + return __riscv_vfncvt_f_f_q_f8e4m3mf2(vs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i8> ... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/172630 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
