================
@@ -4282,6 +4283,72 @@ mlir::LogicalResult
CIRToLLVMAwaitOpLowering::matchAndRewrite(
return mlir::failure();
}
+mlir::LogicalResult CIRToLLVMCpuIdOpLowering::matchAndRewrite(
+ cir::CpuIdOp op, OpAdaptor adaptor,
+ mlir::ConversionPatternRewriter &rewriter) const {
+ mlir::Type i32Ty = rewriter.getI32Type();
+ mlir::Type i64Ty = rewriter.getI64Type();
+ mlir::Type i32PtrTy = mlir::LLVM::LLVMPointerType::get(i32Ty.getContext(),
0);
+
+ mlir::Type cpuidRetTy = mlir::LLVM::LLVMStructType::getLiteral(
+ rewriter.getContext(), {i32Ty, i32Ty, i32Ty, i32Ty});
+
+ mlir::Value funcId = adaptor.getFunctionId();
+ mlir::Value subFuncId = adaptor.getSubFunctionId();
+ std::array<mlir::Value, 2> operands{funcId, subFuncId};
+
+ StringRef asmString, constraints;
+ mlir::ModuleOp moduleOp = op->getParentOfType<mlir::ModuleOp>();
+ llvm::Triple triple(
+ mlir::cast<mlir::StringAttr>(
+ moduleOp->getAttr(cir::CIRDialect::getTripleAttrName()))
+ .getValue());
+ if (triple.getArch() == llvm::Triple::x86) {
+ asmString = "cpuid";
+ constraints = "={ax},={bx},={cx},={dx},{ax},{cx}";
+ } else {
+ // x86-64 uses %rbx as the base register, so preserve it.
+ asmString = "xchgq %rbx, ${1:q}\n"
+ "cpuid\n"
+ "xchgq %rbx, ${1:q}";
+ constraints = "={ax},=r,={cx},={dx},0,2";
+ }
+
+ mlir::Value inlineAsm =
+ mlir::LLVM::InlineAsmOp::create(
+ rewriter, op.getLoc(), cpuidRetTy, mlir::ValueRange(operands),
----------------
andykaylor wrote:
Does this work?
```suggestion
rewriter, op.getLoc(), cpuidRetTy, {funcId, subFuncId},
```
https://github.com/llvm/llvm-project/pull/173197
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