https://github.com/artagnon created https://github.com/llvm/llvm-project/pull/176071
A GCC patch has been landed, which can be used as a reference for the architectural features of tt-ascalon-d8. The patch is missing Zvfbfmin (reported to GCC patch author), but we should align the architectural features in LLVM with that tested patch otherwise. Ref: https://gcc.gnu.org/pipermail/gcc-patches/2026-January/705300.html >From 1797bc85f8f76490829f00bc0b9f6edabbb95cf2 Mon Sep 17 00:00:00 2001 From: Ramkumar Ramachandra <[email protected]> Date: Wed, 14 Jan 2026 12:14:51 +0000 Subject: [PATCH] [RISCV] Add missing arch features of tt-ascalon-d8 A GCC patch has been landed, which can be used as a reference for the architectural features of tt-ascalon-d8. The patch is missing Zvfbfmin (reported to GCC patch author), but we should align the architectural features in LLVM with that tested patch otherwise. Ref: https://gcc.gnu.org/pipermail/gcc-patches/2026-January/705300.html --- clang/test/Driver/riscv-cpus.c | 7 +++++++ llvm/lib/Target/RISCV/RISCVProcessors.td | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 5d5fdd72baedb..5755e7a786ea8 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -231,6 +231,7 @@ // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zba" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zbb" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zbs" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zkr" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zkt" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbb" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbc" @@ -255,10 +256,16 @@ // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl256b" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl32b" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl64b" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+smaia" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+smmpm" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+smnpm" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+smrnmi" +// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+smstateen" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+sscofpmf" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svinval" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svnapot" // MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svpbmt" +// MCPU-TT-ASCALON-D8-SAME: "-target-abi" "lp64d" // RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=veyron-v1 | FileCheck -check-prefix=MCPU-VEYRON-V1 %s // MCPU-VEYRON-V1: "-target-cpu" "veyron-v1" diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 64328a7be21f2..687539e71b84b 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -106,6 +106,7 @@ def GENERIC : RISCVTuneProcessorModel<"generic", NoSchedModel>, GenericTuneInfo; def GENERIC_OOO : RISCVTuneProcessorModel<"generic-ooo", GenericOOOModel>, GenericTuneInfo; +// clang-format off def MIPS_P8700 : RISCVProcessorModel<"mips-p8700", MIPSP8700Model, [Feature64Bit, @@ -619,10 +620,15 @@ def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8", TTAscalonD8Model, !listconcat(RVA23S64Features, [FeatureStdExtSmaia, + FeatureStdExtSmmpm, + FeatureStdExtSmnpm, + FeatureStdExtSmrnmi, + FeatureStdExtSmstateen, FeatureStdExtSsaia, FeatureStdExtSsstrict, FeatureStdExtZfbfmin, FeatureStdExtZfh, + FeatureStdExtZkr, FeatureStdExtZvbc, FeatureStdExtZvfbfmin, FeatureStdExtZvfbfwma, @@ -897,3 +903,4 @@ def AINEKKO_ERBIUM : RISCVProcessorModel<"an-erbium", FeatureStdExtF, FeatureStdExtC, FeatureVendorXAIFET]>; +// clang-format on _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
