Author: Mark Zhuang Date: 2026-01-26T15:24:56+08:00 New Revision: a53daac6f68fa23584758e437221f27cdffd11ed
URL: https://github.com/llvm/llvm-project/commit/a53daac6f68fa23584758e437221f27cdffd11ed DIFF: https://github.com/llvm/llvm-project/commit/a53daac6f68fa23584758e437221f27cdffd11ed.diff LOG: [RISCV] Add Spacemit X100 processor definition (#173988) SpacemiT X100 is a 4-issue, out-of-order, RVA23 processor https://www.spacemit.com/en/spacemit-x100-core/ Added: clang/test/Driver/print-enabled-extensions/riscv-spacemit-x100.c Modified: clang/test/Driver/riscv-cpus.c clang/test/Misc/target-invalid-cpu-note/riscv.c llvm/docs/ReleaseNotes.md llvm/lib/Target/RISCV/RISCVProcessors.td Removed: ################################################################################ diff --git a/clang/test/Driver/print-enabled-extensions/riscv-spacemit-x100.c b/clang/test/Driver/print-enabled-extensions/riscv-spacemit-x100.c new file mode 100644 index 0000000000000..e1d7ac6f2d781 --- /dev/null +++ b/clang/test/Driver/print-enabled-extensions/riscv-spacemit-x100.c @@ -0,0 +1,83 @@ +// REQUIRES: riscv-registered-target +// RUN: %clang --target=riscv64 -mcpu=spacemit-x100 --print-enabled-extensions | FileCheck %s + +// CHECK: Extensions enabled for the given RISC-V target +// CHECK-EMPTY: +// CHECK-NEXT: Name Version Description +// CHECK-NEXT: i 2.1 'I' (Base Integer Instruction Set) +// CHECK-NEXT: m 2.0 'M' (Integer Multiplication and Division) +// CHECK-NEXT: a 2.1 'A' (Atomic Instructions) +// CHECK-NEXT: f 2.2 'F' (Single-Precision Floating-Point) +// CHECK-NEXT: d 2.2 'D' (Double-Precision Floating-Point) +// CHECK-NEXT: c 2.0 'C' (Compressed Instructions) +// CHECK-NEXT: b 1.0 'B' (the collection of the Zba, Zbb, Zbs extensions) +// CHECK-NEXT: v 1.0 'V' (Vector Extension for Application Processors) +// CHECK-NEXT: zic64b 1.0 'Zic64b' (Cache Block Size Is 64 Bytes) +// CHECK-NEXT: zicbom 1.0 'Zicbom' (Cache-Block Management Instructions) +// CHECK-NEXT: zicbop 1.0 'Zicbop' (Cache-Block Prefetch Instructions) +// CHECK-NEXT: zicboz 1.0 'Zicboz' (Cache-Block Zero Instructions) +// CHECK-NEXT: ziccamoa 1.0 'Ziccamoa' (Main Memory Supports All Atomics in A) +// CHECK-NEXT: ziccif 1.0 'Ziccif' (Main Memory Supports Instruction Fetch with Atomicity Requirement) +// CHECK-NEXT: zicclsm 1.0 'Zicclsm' (Main Memory Supports Misaligned Loads/Stores) +// CHECK-NEXT: ziccrse 1.0 'Ziccrse' (Main Memory Supports Forward Progress on LR/SC Sequences) +// CHECK-NEXT: zicntr 2.0 'Zicntr' (Base Counters and Timers) +// CHECK-NEXT: zicond 1.0 'Zicond' (Integer Conditional Operations) +// CHECK-NEXT: zicsr 2.0 'Zicsr' (CSRs) +// CHECK-NEXT: zihintntl 1.0 'Zihintntl' (Non-Temporal Locality Hints) +// CHECK-NEXT: zihintpause 2.0 'Zihintpause' (Pause Hint) +// CHECK-NEXT: zihpm 2.0 'Zihpm' (Hardware Performance Counters) +// CHECK-NEXT: zimop 1.0 'Zimop' (May-Be-Operations) +// CHECK-NEXT: zmmul 1.0 'Zmmul' (Integer Multiplication) +// CHECK-NEXT: za64rs 1.0 'Za64rs' (Reservation Set Size of at Most 64 Bytes) +// CHECK-NEXT: zaamo 1.0 'Zaamo' (Atomic Memory Operations) +// CHECK-NEXT: zalrsc 1.0 'Zalrsc' (Load-Reserved/Store-Conditional) +// CHECK-NEXT: zawrs 1.0 'Zawrs' (Wait on Reservation Set) +// CHECK-NEXT: zfa 1.0 'Zfa' (Additional Floating-Point) +// CHECK-NEXT: zfbfmin 1.0 'Zfbfmin' (Scalar BF16 Converts) +// CHECK-NEXT: zfh 1.0 'Zfh' (Half-Precision Floating-Point) +// CHECK-NEXT: zfhmin 1.0 'Zfhmin' (Half-Precision Floating-Point Minimal) +// CHECK-NEXT: zca 1.0 'Zca' (part of the C extension, excluding compressed floating point loads/stores) +// CHECK-NEXT: zcb 1.0 'Zcb' (Compressed basic bit manipulation instructions) +// CHECK-NEXT: zcd 1.0 'Zcd' (Compressed Double-Precision Floating-Point Instructions) +// CHECK-NEXT: zcmop 1.0 'Zcmop' (Compressed May-Be-Operations) +// CHECK-NEXT: zba 1.0 'Zba' (Address Generation Instructions) +// CHECK-NEXT: zbb 1.0 'Zbb' (Basic Bit-Manipulation) +// CHECK-NEXT: zbc 1.0 'Zbc' (Carry-Less Multiplication) +// CHECK-NEXT: zbkc 1.0 'Zbkc' (Carry-less multiply instructions for Cryptography) +// CHECK-NEXT: zbs 1.0 'Zbs' (Single-Bit Instructions) +// CHECK-NEXT: zkt 1.0 'Zkt' (Data Independent Execution Latency) +// CHECK-NEXT: zvbb 1.0 'Zvbb' (Vector basic bit-manipulation instructions) +// CHECK-NEXT: zvbc 1.0 'Zvbc' (Vector Carryless Multiplication) +// CHECK-NEXT: zve32f 1.0 'Zve32f' (Vector Extensions for Embedded Processors with maximal 32 EEW and F extension) +// CHECK-NEXT: zve32x 1.0 'Zve32x' (Vector Extensions for Embedded Processors with maximal 32 EEW) +// CHECK-NEXT: zve64d 1.0 'Zve64d' (Vector Extensions for Embedded Processors with maximal 64 EEW, F and D extension) +// CHECK-NEXT: zve64f 1.0 'Zve64f' (Vector Extensions for Embedded Processors with maximal 64 EEW and F extension) +// CHECK-NEXT: zve64x 1.0 'Zve64x' (Vector Extensions for Embedded Processors with maximal 64 EEW) +// CHECK-NEXT: zvfbfmin 1.0 'Zvfbfmin' (Vector BF16 Converts) +// CHECK-NEXT: zvfbfwma 1.0 'Zvfbfwma' (Vector BF16 widening mul-add) +// CHECK-NEXT: zvfh 1.0 'Zvfh' (Vector Half-Precision Floating-Point) +// CHECK-NEXT: zvfhmin 1.0 'Zvfhmin' (Vector Half-Precision Floating-Point Minimal) +// CHECK-NEXT: zvkb 1.0 'Zvkb' (Vector Bit-manipulation used in Cryptography) +// CHECK-NEXT: zvkg 1.0 'Zvkg' (Vector GCM instructions for Cryptography) +// CHECK-NEXT: zvkn 1.0 'Zvkn' (shorthand for 'Zvkned', 'Zvknhb', 'Zvkb', and 'Zvkt') +// CHECK-NEXT: zvknc 1.0 'Zvknc' (shorthand for 'Zvknc' and 'Zvbc') +// CHECK-NEXT: zvkned 1.0 'Zvkned' (Vector AES Encryption & Decryption (Single Round)) +// CHECK-NEXT: zvkng 1.0 'Zvkng' (shorthand for 'Zvkn' and 'Zvkg') +// CHECK-NEXT: zvknha 1.0 'Zvknha' (Vector SHA-2 (SHA-256 only)) +// CHECK-NEXT: zvknhb 1.0 'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512)) +// CHECK-NEXT: zvks 1.0 'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt') +// CHECK-NEXT: zvksc 1.0 'Zvksc' (shorthand for 'Zvks' and 'Zvbc') +// CHECK-NEXT: zvksed 1.0 'Zvksed' (SM4 Block Cipher Instructions) +// CHECK-NEXT: zvksg 1.0 'Zvksg' (shorthand for 'Zvks' and 'Zvkg') +// CHECK-NEXT: zvksh 1.0 'Zvksh' (SM3 Hash Function Instructions) +// CHECK-NEXT: zvkt 1.0 'Zvkt' (Vector Data-Independent Execution Latency) +// CHECK-NEXT: zvl128b 1.0 'Zvl128b' (Minimum Vector Length 128) +// CHECK-NEXT: zvl256b 1.0 'Zvl256b' (Minimum Vector Length 256) +// CHECK-NEXT: zvl32b 1.0 'Zvl32b' (Minimum Vector Length 32) +// CHECK-NEXT: zvl64b 1.0 'Zvl64b' (Minimum Vector Length 64) +// CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode Pointer Masking) +// CHECK-NEXT: xsmtvdot 1.0 'XSMTVDot' (SpacemiT Vector Dot Product Extension) +// CHECK-EMPTY: +// CHECK-NEXT: Experimental extensions +// CHECK-EMPTY: +// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbc1p0_zbkc1p0_zbs1p0_zkt1p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfbfwma1p0_zvfh1p0_zvfhmin1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_supm1p0_xsmtvdot1p0 diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 5755e7a786ea8..46f2c390b6efe 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -160,6 +160,14 @@ // MCPU-SPACEMIT-X60-SAME: "-target-feature" "+xsmtvdot" // MCPU-SPACEMIT-X60-SAME: "-target-abi" "lp64d" +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x100 | FileCheck -check-prefix=MCPU-SPACEMIT-X100 %s +// MCPU-SPACEMIT-X100: "-target-cpu" "spacemit-x100" +// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-spacemit-x100.c` +// MCPU-SPACEMIT-X100-SAME: "-target-abi" "lp64d" + +// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=spacemit-x100 | FileCheck -check-prefix=MTUNE-SPACEMIT-X100 %s +// MTUNE-SPACEMIT-X100: "-tune-cpu" "spacemit-x100" + // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string. // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c index 066ea26b834bc..ca46f1d1e9a06 100644 --- a/clang/test/Misc/target-invalid-cpu-note/riscv.c +++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c @@ -50,6 +50,7 @@ // RISCV64-SAME: {{^}}, sifive-x280 // RISCV64-SAME: {{^}}, sifive-x390 // RISCV64-SAME: {{^}}, spacemit-x60 +// RISCV64-SAME: {{^}}, spacemit-x100 // RISCV64-SAME: {{^}}, syntacore-scr3-rv64 // RISCV64-SAME: {{^}}, syntacore-scr4-rv64 // RISCV64-SAME: {{^}}, syntacore-scr5-rv64 @@ -113,6 +114,7 @@ // TUNE-RISCV64-SAME: {{^}}, sifive-x280 // TUNE-RISCV64-SAME: {{^}}, sifive-x390 // TUNE-RISCV64-SAME: {{^}}, spacemit-x60 +// TUNE-RISCV64-SAME: {{^}}, spacemit-x100 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr3-rv64 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr4-rv64 // TUNE-RISCV64-SAME: {{^}}, syntacore-scr5-rv64 diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 74316ccdcaabf..3511271b0f34c 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -121,6 +121,7 @@ Changes to the RISC-V Backend ----------------------------- * `llvm-objdump` now has support for `--symbolize-operands` with RISC-V. +* `-mcpu=spacemit-x100` was added. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index 687539e71b84b..f7bc3b28fb3a4 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -767,6 +767,34 @@ def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60", let MImpID = 0x1000000049772200; } +def SPACEMIT_X100 : RISCVProcessorModel<"spacemit-x100", + NoSchedModel, + !listconcat(RVA23U64Features, + [FeatureStdExtZbc, + FeatureStdExtZbkc, + FeatureStdExtZcd, + FeatureStdExtZfbfmin, + FeatureStdExtZfh, + FeatureStdExtZvbc, + FeatureStdExtZvfbfwma, + FeatureStdExtZvfh, + FeatureStdExtZvkng, + FeatureStdExtZvknha, + FeatureStdExtZvksc, + FeatureStdExtZvksg, + FeatureStdExtZvl256b, + FeatureVendorXSMTVDot, + FeatureUnalignedScalarMem]), + [TuneDLenFactor2, + TuneOptimizedNF2SegmentLoadStore, + TuneOptimizedNF3SegmentLoadStore, + TuneOptimizedNF4SegmentLoadStore, + TuneVXRMPipelineFlush]> { + let MVendorID = 0x710; + let MArchID = 0x8000000058000002; + let MImpID = 0x33d8a600; +} + def RP2350_HAZARD3 : RISCVProcessorModel<"rp2350-hazard3", NoSchedModel, [Feature32Bit, _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
