llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-llvm-transforms Author: Brandon Wu (4vtomat) <details> <summary>Changes</summary> The renaming PR is here: https://github.com/riscv/riscv-isa-manual/pull/2576 --- Patch is 817.79 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/179393.diff 65 Files Affected: - (modified) clang/include/clang/Basic/riscv_vector.td (+8-8) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c (+51-52) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c (+51-51) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vv.c (+118) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4su_vx.c (+41-41) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vv.c (+42-42) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4u_vx.c (+41-41) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4us_vx.c (+117) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vv.c (+51-52) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4_vx.c (+51-51) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vv.c (+118) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4su_vx.c (+41-41) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vv.c (+42-42) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4u_vx.c (+41-41) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/overloaded/vdota4us_vx.c (+117) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vv.c (+103-112) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4_vx.c (+101-104) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vv.c (+232) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4su_vx.c (+81-81) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vv.c (+100-94) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4u_vx.c (+89-89) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/non-overloaded/vdota4us_vx.c (+230) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vv.c (+103-112) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4_vx.c (+101-104) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vv.c (+232) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4su_vx.c (+81-81) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vv.c (+100-94) - (renamed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4u_vx.c (+89-89) - (added) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/policy/overloaded/vdota4us_vx.c (+230) - (removed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdot_vv.c (-117) - (removed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdot_vx.c (-117) - (removed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdot_vv.c (-117) - (removed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/overloaded/vqdot_vx.c (-117) - (removed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdot_vv.c (-229) - (removed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/non-overloaded/vqdot_vx.c (-227) - (removed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdot_vv.c (-229) - (removed) clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/policy/overloaded/vqdot_vx.c (-227) - (modified) clang/test/Driver/print-supported-extensions-riscv.c (+1-1) - (modified) clang/test/Preprocessor/riscv-target-features.c (+6-6) - (modified) llvm/docs/RISCVUsage.rst (+1-1) - (modified) llvm/include/llvm/IR/IntrinsicsRISCV.td (+10-10) - (modified) llvm/lib/Target/RISCV/RISCVFeatures.td (+4-4) - (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+24-24) - (modified) llvm/lib/Target/RISCV/RISCVInstrInfo.td (+1-1) - (renamed) llvm/lib/Target/RISCV/RISCVInstrInfoZvdot4a8i.td (+34-34) - (modified) llvm/lib/Target/RISCV/RISCVSelectionDAGInfo.cpp (+3-3) - (modified) llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp (+3-3) - (modified) llvm/test/CodeGen/RISCV/attributes.ll (+4-4) - (modified) llvm/test/CodeGen/RISCV/features-info.ll (+1-1) - (modified) llvm/test/CodeGen/RISCV/pr148084.ll (+1-1) - (renamed) llvm/test/CodeGen/RISCV/rvv/fixed-vectors-zvdot4a8i.ll (+131-131) - (renamed) llvm/test/CodeGen/RISCV/rvv/vdota4.ll (+82-82) - (added) llvm/test/CodeGen/RISCV/rvv/vdota4su.ll (+337) - (renamed) llvm/test/CodeGen/RISCV/rvv/vdota4u.ll (+82-82) - (added) llvm/test/CodeGen/RISCV/rvv/vdota4us.ll (+170) - (removed) llvm/test/CodeGen/RISCV/rvv/vqdot.ll (-337) - (removed) llvm/test/CodeGen/RISCV/rvv/vqdotus.ll (-170) - (renamed) llvm/test/CodeGen/RISCV/rvv/zvdot4a8i-sdnode.ll (+74-74) - (modified) llvm/test/DebugInfo/RISCV/relax_dwo_ranges.ll (+3-3) - (modified) llvm/test/MC/RISCV/attribute-arch.s (+2-2) - (renamed) llvm/test/MC/RISCV/rvv/zvdot4a8i-invalid.s (+5-5) - (added) llvm/test/MC/RISCV/rvv/zvdot4a8i.s (+93) - (removed) llvm/test/MC/RISCV/rvv/zvqdotq.s (-93) - (modified) llvm/test/Transforms/LoopVectorize/RISCV/partial-reduce-dot-product.ll (+287-287) - (modified) llvm/unittests/TargetParser/RISCVISAInfoTest.cpp (+1-1) ``````````diff diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index c899dc70fc0b7..718725555c845 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -2085,8 +2085,8 @@ let UnMaskedPolicyScheme = HasPolicyOperand, HasMasked = false in { } } -// Zvqdotq -multiclass RVVVQDOTQBuiltinSet<list<list<string>> suffixes_prototypes> { +// Zvdot4a8i +multiclass RVVVDOTA4QBuiltinSet<list<list<string>> suffixes_prototypes> { let UnMaskedPolicyScheme = HasPolicyOperand, HasMaskedOffOperand = false, OverloadedName = NAME, @@ -2095,14 +2095,14 @@ multiclass RVVVQDOTQBuiltinSet<list<list<string>> suffixes_prototypes> { } } -// Only SEW=32 is defined for zvqdotq so far, and since inputs are in fact four +// Only SEW=32 is defined for zvdot4a8i so far, and since inputs are in fact four // 8-bit integer bundles, we use unsigned type to represent all of them -let RequiredFeatures = ["zvqdotq"] in { - defm vqdot : RVVVQDOTQBuiltinSet<[["vv", "v", "vv(FixedSEW:8)v(FixedSEW:8)v"], +let RequiredFeatures = ["zvdot4a8i"] in { + defm vdota4 : RVVVDOTA4QBuiltinSet<[["vv", "v", "vv(FixedSEW:8)v(FixedSEW:8)v"], ["vx", "v", "vv(FixedSEW:8)vUe"]]>; - defm vqdotu : RVVVQDOTQBuiltinSet<[["vv", "Uv", "UvUv(FixedSEW:8)Uv(FixedSEW:8)Uv"], + defm vdota4u : RVVVDOTA4QBuiltinSet<[["vv", "Uv", "UvUv(FixedSEW:8)Uv(FixedSEW:8)Uv"], ["vx", "Uv", "UvUv(FixedSEW:8)UvUe"]]>; - defm vqdotsu : RVVVQDOTQBuiltinSet<[["vv", "v", "vv(FixedSEW:8)v(FixedSEW:8)Uv"], + defm vdota4su : RVVVDOTA4QBuiltinSet<[["vv", "v", "vv(FixedSEW:8)v(FixedSEW:8)Uv"], ["vx", "v", "vv(FixedSEW:8)vUe"]]>; - defm vqdotus : RVVVQDOTQBuiltinSet<[["vx", "v", "vv(FixedSEW:8)UvUe"]]>; + defm vdota4us : RVVVDOTA4QBuiltinSet<[["vx", "v", "vv(FixedSEW:8)UvUe"]]>; } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotu_vv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c similarity index 65% rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotu_vv.c rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c index cd43ecf51ee11..2c95e12dbd0ab 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotu_vv.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vv.c @@ -1,118 +1,117 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: FileCheck --check-prefix=CHECK-RV64 %s #include <sifive_vector.h> -// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2( +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2( // CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // -vuint32mf2_t test_vqdotu_vv_u32mf2(vuint32mf2_t vd, vuint8mf2_t vs2, - vuint8mf2_t vs1, size_t vl) { - return __riscv_vqdotu_vv_u32mf2(vd, vs2, vs1, vl); +vint32mf2_t test_vdota4_vv_i32mf2(vint32mf2_t vd, vint8mf2_t vs2, vint8mf2_t vs1, + size_t vl) { + return __riscv_vdota4_vv_i32mf2(vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1( +// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1( // CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // -vuint32m1_t test_vqdotu_vv_u32m1(vuint32m1_t vd, vuint8m1_t vs2, vuint8m1_t vs1, - size_t vl) { - return __riscv_vqdotu_vv_u32m1(vd, vs2, vs1, vl); +vint32m1_t test_vdota4_vv_i32m1(vint32m1_t vd, vint8m1_t vs2, vint8m1_t vs1, + size_t vl) { + return __riscv_vdota4_vv_i32m1(vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2( +// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2( // CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // -vuint32m2_t test_vqdotu_vv_u32m2(vuint32m2_t vd, vuint8m2_t vs2, vuint8m2_t vs1, - size_t vl) { - return __riscv_vqdotu_vv_u32m2(vd, vs2, vs1, vl); +vint32m2_t test_vdota4_vv_i32m2(vint32m2_t vd, vint8m2_t vs2, vint8m2_t vs1, + size_t vl) { + return __riscv_vdota4_vv_i32m2(vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4( +// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4( // CHECK-RV64-SAME: <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // -vuint32m4_t test_vqdotu_vv_u32m4(vuint32m4_t vd, vuint8m4_t vs2, vuint8m4_t vs1, - size_t vl) { - return __riscv_vqdotu_vv_u32m4(vd, vs2, vs1, vl); +vint32m4_t test_vdota4_vv_i32m4(vint32m4_t vd, vint8m4_t vs2, vint8m4_t vs1, + size_t vl) { + return __riscv_vdota4_vv_i32m4(vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8( +// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8( // CHECK-RV64-SAME: <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // -vuint32m8_t test_vqdotu_vv_u32m8(vuint32m8_t vd, vuint8m8_t vs2, vuint8m8_t vs1, - size_t vl) { - return __riscv_vqdotu_vv_u32m8(vd, vs2, vs1, vl); +vint32m8_t test_vdota4_vv_i32m8(vint32m8_t vd, vint8m8_t vs2, vint8m8_t vs1, + size_t vl) { + return __riscv_vdota4_vv_i32m8(vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vv_u32mf2_m( +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vv_i32mf2_m( // CHECK-RV64-SAME: <vscale x 1 x i1> [[VM:%.*]], <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], <vscale x 4 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.mask.nxv1i32.nxv4i8.nxv4i8.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], <vscale x 4 x i8> [[VS1]], <vscale x 1 x i1> [[VM]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // -vuint32mf2_t test_vqdotu_vv_u32mf2_m(vbool64_t vm, vuint32mf2_t vd, - vuint8mf2_t vs2, vuint8mf2_t vs1, - size_t vl) { - return __riscv_vqdotu_vv_u32mf2_m(vm, vd, vs2, vs1, vl); +vint32mf2_t test_vdota4_vv_i32mf2_m(vbool64_t vm, vint32mf2_t vd, vint8mf2_t vs2, + vint8mf2_t vs1, size_t vl) { + return __riscv_vdota4_vv_i32mf2_m(vm, vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vv_u32m1_m( +// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vv_i32m1_m( // CHECK-RV64-SAME: <vscale x 2 x i1> [[VM:%.*]], <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], <vscale x 8 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.mask.nxv2i32.nxv8i8.nxv8i8.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], <vscale x 8 x i8> [[VS1]], <vscale x 2 x i1> [[VM]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // -vuint32m1_t test_vqdotu_vv_u32m1_m(vbool32_t vm, vuint32m1_t vd, vuint8m1_t vs2, - vuint8m1_t vs1, size_t vl) { - return __riscv_vqdotu_vv_u32m1_m(vm, vd, vs2, vs1, vl); +vint32m1_t test_vdota4_vv_i32m1_m(vbool32_t vm, vint32m1_t vd, vint8m1_t vs2, + vint8m1_t vs1, size_t vl) { + return __riscv_vdota4_vv_i32m1_m(vm, vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vv_u32m2_m( +// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vv_i32m2_m( // CHECK-RV64-SAME: <vscale x 4 x i1> [[VM:%.*]], <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], <vscale x 16 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.mask.nxv4i32.nxv16i8.nxv16i8.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], <vscale x 16 x i8> [[VS1]], <vscale x 4 x i1> [[VM]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // -vuint32m2_t test_vqdotu_vv_u32m2_m(vbool16_t vm, vuint32m2_t vd, vuint8m2_t vs2, - vuint8m2_t vs1, size_t vl) { - return __riscv_vqdotu_vv_u32m2_m(vm, vd, vs2, vs1, vl); +vint32m2_t test_vdota4_vv_i32m2_m(vbool16_t vm, vint32m2_t vd, vint8m2_t vs2, + vint8m2_t vs1, size_t vl) { + return __riscv_vdota4_vv_i32m2_m(vm, vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vqdotu_vv_u32m4_m( +// CHECK-RV64-LABEL: define dso_local <vscale x 8 x i32> @test_vdota4_vv_i32m4_m( // CHECK-RV64-SAME: <vscale x 8 x i1> [[VM:%.*]], <vscale x 8 x i32> [[VD:%.*]], <vscale x 32 x i8> [[VS2:%.*]], <vscale x 32 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vqdotu.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i32> @llvm.riscv.vdota4.mask.nxv8i32.nxv32i8.nxv32i8.i64(<vscale x 8 x i32> [[VD]], <vscale x 32 x i8> [[VS2]], <vscale x 32 x i8> [[VS1]], <vscale x 8 x i1> [[VM]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 8 x i32> [[TMP0]] // -vuint32m4_t test_vqdotu_vv_u32m4_m(vbool8_t vm, vuint32m4_t vd, vuint8m4_t vs2, - vuint8m4_t vs1, size_t vl) { - return __riscv_vqdotu_vv_u32m4_m(vm, vd, vs2, vs1, vl); +vint32m4_t test_vdota4_vv_i32m4_m(vbool8_t vm, vint32m4_t vd, vint8m4_t vs2, + vint8m4_t vs1, size_t vl) { + return __riscv_vdota4_vv_i32m4_m(vm, vd, vs2, vs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vqdotu_vv_u32m8_m( +// CHECK-RV64-LABEL: define dso_local <vscale x 16 x i32> @test_vdota4_vv_i32m8_m( // CHECK-RV64-SAME: <vscale x 16 x i1> [[VM:%.*]], <vscale x 16 x i32> [[VD:%.*]], <vscale x 64 x i8> [[VS2:%.*]], <vscale x 64 x i8> [[VS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vqdotu.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i32> @llvm.riscv.vdota4.mask.nxv16i32.nxv64i8.nxv64i8.i64(<vscale x 16 x i32> [[VD]], <vscale x 64 x i8> [[VS2]], <vscale x 64 x i8> [[VS1]], <vscale x 16 x i1> [[VM]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 16 x i32> [[TMP0]] // -vuint32m8_t test_vqdotu_vv_u32m8_m(vbool4_t vm, vuint32m8_t vd, vuint8m8_t vs2, - vuint8m8_t vs1, size_t vl) { - return __riscv_vqdotu_vv_u32m8_m(vm, vd, vs2, vs1, vl); +vint32m8_t test_vdota4_vv_i32m8_m(vbool4_t vm, vint32m8_t vd, vint8m8_t vs2, + vint8m8_t vs1, size_t vl) { + return __riscv_vdota4_vv_i32m8_m(vm, vd, vs2, vs1, vl); } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotu_vx.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c similarity index 65% rename from clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotu_vx.c rename to clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c index a4c446cc92949..421a96b2191b0 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvqdotq/non-policy/non-overloaded/vqdotu_vx.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/zvdot4a8i/non-policy/non-overloaded/vdota4_vx.c @@ -1,117 +1,117 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvqdotq -disable-O0-optnone \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +experimental-zvdot4a8i -disable-O0-optnone \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: FileCheck --check-prefix=CHECK-RV64 %s #include <sifive_vector.h> -// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vqdotu_vx_u32mf2( +// CHECK-RV64-LABEL: define dso_local <vscale x 1 x i32> @test_vdota4_vx_i32mf2( // CHECK-RV64-SAME: <vscale x 1 x i32> [[VD:%.*]], <vscale x 4 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vqdotu.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i32> @llvm.riscv.vdota4.nxv1i32.nxv4i8.i32.i64(<vscale x 1 x i32> [[VD]], <vscale x 4 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 1 x i32> [[TMP0]] // -vuint32mf2_t test_vqdotu_vx_u32mf2(vuint32mf2_t vd, vuint8mf2_t vs2, - uint32_t rs1, size_t vl) { - return __riscv_vqdotu_vx_u32mf2(vd, vs2, rs1, vl); +vint32mf2_t test_vdota4_vx_i32mf2(vint32mf2_t vd, vint8mf2_t vs2, uint32_t rs1, + size_t vl) { + return __riscv_vdota4_vx_i32mf2(vd, vs2, rs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vqdotu_vx_u32m1( +// CHECK-RV64-LABEL: define dso_local <vscale x 2 x i32> @test_vdota4_vx_i32m1( // CHECK-RV64-SAME: <vscale x 2 x i32> [[VD:%.*]], <vscale x 8 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vqdotu.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i32> @llvm.riscv.vdota4.nxv2i32.nxv8i8.i32.i64(<vscale x 2 x i32> [[VD]], <vscale x 8 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 2 x i32> [[TMP0]] // -vuint32m1_t test_vqdotu_vx_u32m1(vuint32m1_t vd, vuint8m1_t vs2, uint32_t rs1, - size_t vl) { - return __riscv_vqdotu_vx_u32m1(vd, vs2, rs1, vl); +vint32m1_t test_vdota4_vx_i32m1(vint32m1_t vd, vint8m1_t vs2, uint32_t rs1, + size_t vl) { + return __riscv_vdota4_vx_i32m1(vd, vs2, rs1, vl); } -// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vqdotu_vx_u32m2( +// CHECK-RV64-LABEL: define dso_local <vscale x 4 x i32> @test_vdota4_vx_i32m2( // CHECK-RV64-SAME: <vscale x 4 x i32> [[VD:%.*]], <vscale x 16 x i8> [[VS2:%.*]], i32 noundef signext [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vqdotu.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i32> @llvm.riscv.vdota4.nxv4i32.nxv16i8.i32.i64(<vscale x 4 x i32> [[VD]], <vscale x 16 x i8> [[VS2]], i32 [[RS1]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: ret <vscale x 4 x i32> [[TMP0]] // -vuint32m2_t test_vqdotu_vx_u32m2(vuint32m2_t vd, vuint8m2_t vs2, uint32_t rs1, - size_t vl) { - return __riscv_vqdotu_vx_u32m2(vd, vs2, rs1, vl); +vint32m2_t test_vdota4_vx_i32m2(vint32m2_t vd, vint8... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/179393 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
