https://github.com/kmclaughlin-arm created https://github.com/llvm/llvm-project/pull/179709
This patch adds support in Clang for the PRFM IR instruction, by adding the following builtin: ``` void __pldir(void const *addr); ``` This builtin is described in the following ACLE proposal: https://github.com/ARM-software/acle/pull/406 >From 4d8a1332357864bab08899e598ee3909ff7711b4 Mon Sep 17 00:00:00 2001 From: Kerry McLaughlin <[email protected]> Date: Mon, 19 Jan 2026 16:49:57 +0000 Subject: [PATCH] [AArch64] Add support for intent to read prefetch intrinsic This patch adds support in Clang for the PRFM IR instruction, by adding the following builtin: ``` void __pldir(void const *addr); ``` This builtin is described in the following ACLE proposal: https://github.com/ARM-software/acle/pull/406 --- clang/include/clang/Basic/BuiltinsAArch64.def | 2 ++ clang/lib/Headers/arm_acle.h | 1 + clang/test/CodeGen/arm_acle.c | 13 +++++++++++++ clang/test/CodeGen/builtins-arm64.c | 5 +++++ llvm/include/llvm/IR/IntrinsicsAArch64.td | 5 +++++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp | 5 +++++ llvm/lib/Target/AArch64/AArch64SystemOperands.td | 1 + .../Target/AArch64/GISel/AArch64LegalizerInfo.cpp | 6 ++++++ llvm/test/CodeGen/AArch64/arm64-prefetch-ri.ll | 12 ++++++++++++ llvm/test/MC/AArch64/armv9.6a-pcdphint.s | 10 +++++++++- 10 files changed, 59 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/AArch64/arm64-prefetch-ri.ll diff --git a/clang/include/clang/Basic/BuiltinsAArch64.def b/clang/include/clang/Basic/BuiltinsAArch64.def index 5ae5affb51fde..5d7e956b73b87 100644 --- a/clang/include/clang/Basic/BuiltinsAArch64.def +++ b/clang/include/clang/Basic/BuiltinsAArch64.def @@ -96,6 +96,8 @@ TARGET_BUILTIN(__builtin_arm_jcvt, "Zid", "nc", "v8.3a") // Prefetch BUILTIN(__builtin_arm_prefetch, "vvC*UiUiUiUi", "nc") +BUILTIN(__builtin_arm_prefetch_ir, "vvC*", "nc") + // Range Prefetch BUILTIN(__builtin_arm_range_prefetch_x, "vvC*UiUiiUiiz", "n") BUILTIN(__builtin_arm_range_prefetch, "vvC*UiUiWUi", "n") diff --git a/clang/lib/Headers/arm_acle.h b/clang/lib/Headers/arm_acle.h index 622e8f3d6aa7b..9a6b6a837fa5a 100644 --- a/clang/lib/Headers/arm_acle.h +++ b/clang/lib/Headers/arm_acle.h @@ -115,6 +115,7 @@ __swp(uint32_t __x, volatile uint32_t *__p) { #else #define __plix(cache_level, retention_policy, addr) \ __builtin_arm_prefetch(addr, 0, cache_level, retention_policy, 0) +#define __pldir(addr) __builtin_arm_prefetch_ir(addr) #endif /* 7.7 NOP */ diff --git a/clang/test/CodeGen/arm_acle.c b/clang/test/CodeGen/arm_acle.c index 2606ad6dd2ec1..b053778581134 100644 --- a/clang/test/CodeGen/arm_acle.c +++ b/clang/test/CodeGen/arm_acle.c @@ -186,6 +186,19 @@ void test_pldx_range() { #endif +#if defined(__ARM_64BIT_STATE) + +// AArch64-LABEL: @test_pldir( +// AArch64-NEXT: entry: +// AArch64-NEXT: call void @llvm.aarch64.prefetch.ir(ptr null) +// AArch64-NEXT: ret void +// +void test_pldir() { + __pldir(0); +} + +#endif + // AArch32-LABEL: @test_pldx( // AArch32-NEXT: entry: // AArch32-NEXT: call void @llvm.prefetch.p0(ptr null, i32 1, i32 3, i32 1) diff --git a/clang/test/CodeGen/builtins-arm64.c b/clang/test/CodeGen/builtins-arm64.c index c1fd348371f38..3d054c79f1777 100644 --- a/clang/test/CodeGen/builtins-arm64.c +++ b/clang/test/CodeGen/builtins-arm64.c @@ -111,6 +111,11 @@ void range_prefetch_x(void) { // CHECK: call {{.*}} @llvm.aarch64.range.prefetch(ptr null, i32 0, i32 0, i64 0) } +void read_intent_prefetch() { + // CHECK: call {{.*}} @llvm.aarch64.prefetch.ir(ptr null) + __builtin_arm_prefetch_ir(0); +} + __attribute__((target("v8.5a"))) int32_t jcvt(double v) { //CHECK-LABEL: @jcvt( diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index fd56e0e3f9e7b..7f4b7383415c1 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -76,6 +76,11 @@ def int_aarch64_prefetch : Intrinsic<[], ]>, ClangBuiltin<"__builtin_arm_prefetch">; +def int_aarch64_prefetch_ir : Intrinsic<[], [llvm_ptr_ty], + [IntrHasSideEffects, IntrInaccessibleMemOrArgMemOnly, + IntrWillReturn, ReadOnly<ArgIndex<0>>]>, + ClangBuiltin<"__builtin_arm_prefetch_ir">; + def int_aarch64_range_prefetch : Intrinsic<[], [llvm_ptr_ty, llvm_i32_ty, llvm_i32_ty, llvm_i64_ty], [IntrInaccessibleMemOrArgMemOnly, IntrWillReturn, ReadOnly<ArgIndex<0>>, diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 840298ff965e1..d460997a31c9e 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -6279,6 +6279,11 @@ SDValue AArch64TargetLowering::LowerINTRINSIC_VOID(SDValue Op, DAG.getTargetConstant(PrfOp, DL, MVT::i32), Addr, Metadata); } + case Intrinsic::aarch64_prefetch_ir: + return DAG.getNode(AArch64ISD::PREFETCH, DL, MVT::Other, + Op.getOperand(0), // Chain + DAG.getTargetConstant(24, DL, MVT::i32), // Rt + Op.getOperand(2)); // Addr case Intrinsic::aarch64_sme_str: case Intrinsic::aarch64_sme_ldr: { return LowerSMELdrStr(Op, DAG, IntNo == Intrinsic::aarch64_sme_ldr); diff --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td index cb098751fd74d..a1ab0da7b051c 100644 --- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td +++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td @@ -435,6 +435,7 @@ let Requires = [{ {AArch64::FeaturePRFM_SLC} }] in { def : PRFM<"pst", 0b10, "slc", 0b11, "keep", 0b0>; def : PRFM<"pst", 0b10, "slc", 0b11, "strm", 0b1>; } +def : PRFM<"ir", 0b11, "", 0b00, "", 0b0>; //===----------------------------------------------------------------------===// // SVE Prefetch instruction options. diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp index 62f8237dc3b6b..2ed567a1052ca 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp @@ -1769,6 +1769,12 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper, MI.eraseFromParent(); return true; } + case Intrinsic::aarch64_prefetch_ir: { + auto &AddrVal = MI.getOperand(1); + MIB.buildInstr(AArch64::G_AARCH64_PREFETCH).addImm(24).add(AddrVal); + MI.eraseFromParent(); + return true; + } case Intrinsic::aarch64_neon_uaddv: case Intrinsic::aarch64_neon_saddv: case Intrinsic::aarch64_neon_umaxv: diff --git a/llvm/test/CodeGen/AArch64/arm64-prefetch-ri.ll b/llvm/test/CodeGen/AArch64/arm64-prefetch-ri.ll new file mode 100644 index 0000000000000..6ce616ee59b50 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/arm64-prefetch-ri.ll @@ -0,0 +1,12 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=aarch64 -mattr=+v9a -mattr=+pcdphint --global-isel=0 < %s | FileCheck %s +; RUN: llc -mtriple=aarch64 -mattr=+v9a -mattr=+pcdphint --global-isel=1 --global-isel-abort=1 < %s | FileCheck %s + +define void @read_intent_prefetch(ptr %a, i64 %metadata) { +; CHECK-LABEL: read_intent_prefetch: +; CHECK: // %bb.0: +; CHECK-NEXT: prfm ir, [x0] +; CHECK-NEXT: ret + call void @llvm.aarch64.prefetch.ir(ptr %a) + ret void +} diff --git a/llvm/test/MC/AArch64/armv9.6a-pcdphint.s b/llvm/test/MC/AArch64/armv9.6a-pcdphint.s index 8394171740501..b54409abe4a06 100644 --- a/llvm/test/MC/AArch64/armv9.6a-pcdphint.s +++ b/llvm/test/MC/AArch64/armv9.6a-pcdphint.s @@ -3,7 +3,7 @@ // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: | FileCheck %s --check-prefixes=CHECK-ERROR // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+pcdphint < %s \ -// RUN: | llvm-objdump -d --mattr=+pcdphint - | FileCheck %s --check-prefix=CHECK-INST +// RUN: | llvm-objdump -d --mattr=+pcdphint --no-print-imm-hex - | FileCheck %s --check-prefix=CHECK-INST // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+pcdphint < %s \ // RUN: | llvm-objdump -d --mattr=-pcdphint - | FileCheck %s --check-prefix=CHECK-UNKNOWN // Disassemble encoding and check the re-encoding (-show-encoding) matches. @@ -23,3 +23,11 @@ stshh strm // CHECK-ENCODING: encoding: [0x3f,0x96,0x01,0xd5] // CHECK-ERROR: error: instruction requires: pcdphint // CHECK-UNKNOWN: d501963f msr S0_1_C9_C6_1, xzr + +prfm ir, [x0] +// CHECK-INST: prfm ir, [x0] +// CHECK-ENCODING: [0x18,0x00,0x80,0xf9] + +prfm ir, [x2, #800] +// CHECK-INST: prfm ir, [x2, #800] +// CHECK-ENCODING: [0x58,0x90,0x81,0xf9] _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
