chichunchen wrote: > Thanks for this PR. > > Could you summarize what will work after this PR? Does this PR end up > generating vector function variants that will be picked up by the vectorizer? > > > Codegen for AArch64 is not included in this patch. > > Is this unavailable in Clang as well?
1. The goal of this ticket is to generate vector function variants for declare simd. We rely on the vectorizer to make use of these generated variants. The function variants follow the Vector ABI specification described here: https://sourceware.org/glibc/wiki/libmvec?action=AttachFile&do=view&target=VectorABI.txt This is the same approach used by Clang. 2. Clang supports both x86 and AArch64, although its implementation may not strictly follow the most up-to-date Arm Vector ABI specification since the spec came out after Clang's implementation: https://github.com/ARM-software/abi-aa/blob/main/vfabia64/vfabia64.rst For this patch, I focused on x86 to ensure that the lowering to LLVM IR is correct and on the right track. I expect that much of the infrastructure introduced here can be reused for AArch64. However, generating the correct function variants for Arm is significantly more complex and will likely require substantial additional work. https://github.com/llvm/llvm-project/pull/178087 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
