Author: Craig Topper Date: 2026-02-17T21:18:52-08:00 New Revision: a2e14e41cfe41f71a79b21b53fefd26781e4061e
URL: https://github.com/llvm/llvm-project/commit/a2e14e41cfe41f71a79b21b53fefd26781e4061e DIFF: https://github.com/llvm/llvm-project/commit/a2e14e41cfe41f71a79b21b53fefd26781e4061e.diff LOG: [RISCV] Add Xsfmm32a shorthand extension. (#181957) This extension is shorthand for Xsfmm32a8i, Xsfmm32a16f, and Xsfmm32a32f. It was mistakenly left out of an earlier version of the public specification, but is now present. See https://www.sifive.com/document-file/xsfmm-matrix-extensions-specification Added: Modified: clang/test/Driver/print-supported-extensions-riscv.c llvm/lib/Target/RISCV/RISCVFeatures.td llvm/lib/TargetParser/RISCVISAInfo.cpp llvm/test/CodeGen/RISCV/attributes-sifive.ll llvm/test/CodeGen/RISCV/features-info.ll llvm/unittests/TargetParser/RISCVISAInfoTest.cpp Removed: ################################################################################ diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index 3abafb6deafb2..8b6cc22dc1d48 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -204,6 +204,7 @@ // CHECK-NEXT: xsfcease 1.0 'XSfcease' (SiFive sf.cease Instruction) // CHECK-NEXT: xsfmm128t 0.6 'XSfmm128t' (TE=128 configuration) // CHECK-NEXT: xsfmm16t 0.6 'XSfmm16t' (TE=16 configuration) +// CHECK-NEXT: xsfmm32a 0.6 'XSfmm32a' (TEW=32-bit accumulation operands - int: 8b; float: fp16, bf16, fp32) // CHECK-NEXT: xsfmm32a16f 0.6 'XSfmm32a16f' (TEW=32-bit accumulation, operands - float: 16b, widen=2 (IEEE, BF)) // CHECK-NEXT: xsfmm32a32f 0.6 'XSfmm32a32f' (TEW=32-bit accumulation, operands - float: 32b) // CHECK-NEXT: xsfmm32a8f 0.6 'XSfmm32a8f' (TEW=32-bit accumulation, operands - float: fp8) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 1d59c230f261a..094c26007d2fc 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1299,6 +1299,11 @@ def FeatureVendorXSfmm128t "TE=128 configuration", [FeatureVendorXSfmmbase, FeatureStdExtZvl512b], "XSfmmTE", "128">; +def FeatureVendorXSfmm32a + : RISCVExtension<0, 6, + "TEW=32-bit accumulation operands - int: 8b; float: fp16, bf16, fp32", + [FeatureVendorXSfmm32a8i, FeatureVendorXSfmm32a16f, FeatureVendorXSfmm32a32f]>; + def FeatureVendorXSfvqmaccdod : RISCVExtension<1, 0, "SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)", diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index 3d0bc6512ff59..9ebba94419fbc 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -922,8 +922,9 @@ void RISCVISAInfo::updateImplication() { } static constexpr StringLiteral CombineIntoExts[] = { - {"a"}, {"b"}, {"zk"}, {"zkn"}, {"zks"}, {"zvkn"}, - {"zvknc"}, {"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"}, {"xqci"}, + {"a"}, {"b"}, {"zk"}, {"zkn"}, {"zks"}, + {"zvkn"}, {"zvknc"}, {"zvkng"}, {"zvks"}, {"zvksc"}, + {"zvksg"}, {"xqci"}, {"xsfmm32a"}, }; void RISCVISAInfo::updateCombination() { diff --git a/llvm/test/CodeGen/RISCV/attributes-sifive.ll b/llvm/test/CodeGen/RISCV/attributes-sifive.ll index 6731509e48880..8973eb7978096 100644 --- a/llvm/test/CodeGen/RISCV/attributes-sifive.ll +++ b/llvm/test/CodeGen/RISCV/attributes-sifive.ll @@ -23,6 +23,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+xsfmm64a64f %s -o - | FileCheck --check-prefixes=CHECK,RV64XSFMM64A64F %s ; RUN: llc -mtriple=riscv64 -mattr=+xsfmm64t %s -o - | FileCheck --check-prefixes=CHECK,RV64XSFMM64T %s ; RUN: llc -mtriple=riscv64 -mattr=+xsfmmbase %s -o - | FileCheck --check-prefixes=CHECK,RV64XSFMMBASE %s +; RUN: llc -mtriple=riscv64 -mattr=+xsfmm32a %s -o - | FileCheck --check-prefixes=CHECK,RV64XSFMM32A %s +; RUN: llc -mtriple=riscv64 -mattr=+xsfmm32a8i,+xsfmm32a16f,+xsfmm32a32f %s -o - | FileCheck --check-prefixes=CHECK,RV64COMBINEINTOXSFMM32A %s ; CHECK: .attribute 4, 16 @@ -49,6 +51,8 @@ ; RV64XSFMM64A64F: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl32b1p0_zvl64b1p0_xsfmm64a64f0p6_xsfmmbase0p6" ; RV64XSFMM64T: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl128b1p0_zvl256b1p0_zvl32b1p0_zvl64b1p0_xsfmm64t0p6_xsfmmbase0p6" ; RV64XSFMMBASE: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfmmbase0p6" +; RV64XSFMM32A: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xsfmm32a0p6_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm32a8i0p6_xsfmmbase0p6" +; RV64COMBINEINTOXSFMM32A: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvl32b1p0_xsfmm32a0p6_xsfmm32a16f0p6_xsfmm32a32f0p6_xsfmm32a8i0p6_xsfmmbase0p6" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index c2e56061bf579..175bbbe66636b 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -225,6 +225,7 @@ ; CHECK-NEXT: xsfcease - 'XSfcease' (SiFive sf.cease Instruction). ; CHECK-NEXT: xsfmm128t - 'XSfmm128t' (TE=128 configuration). ; CHECK-NEXT: xsfmm16t - 'XSfmm16t' (TE=16 configuration). +; CHECK-NEXT: xsfmm32a - 'XSfmm32a' (TEW=32-bit accumulation operands - int: 8b; float: fp16, bf16, fp32) ; CHECK-NEXT: xsfmm32a16f - 'XSfmm32a16f' (TEW=32-bit accumulation, operands - float: 16b, widen=2 (IEEE, BF)). ; CHECK-NEXT: xsfmm32a32f - 'XSfmm32a32f' (TEW=32-bit accumulation, operands - float: 32b). ; CHECK-NEXT: xsfmm32a8f - 'XSfmm32a8f' (TEW=32-bit accumulation, operands - float: fp8). diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index f266c4b2d800c..7d4d5e076a81c 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1335,6 +1335,7 @@ R"(All available -march extensions for RISC-V xsfcease 1.0 xsfmm128t 0.6 xsfmm16t 0.6 + xsfmm32a 0.6 xsfmm32a16f 0.6 xsfmm32a32f 0.6 xsfmm32a8f 0.6 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
