github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
<details>
<summary>
You can test this locally with the following command:
</summary>
``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h,cl --
clang/test/CodeGenOpenCL/builtins-amdgcn-gfx1250-tensor-load-store.cl
clang/test/SemaOpenCL/builtins-amdgcn-error-gfx1250-param.cl
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
llvm/lib/Target/AMDGPU/AMDGPUInstCombineIntrinsic.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
llvm/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp --diff_from_common_commit
``````````
:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:
</details>
<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index b0a26495c..b2d584899 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -3007,8 +3007,8 @@ void AMDGPUDAGToDAGISel::SelectDSBvhStackIntrinsic(SDNode
*N, unsigned IntrID) {
void AMDGPUDAGToDAGISel::SelectTensorLoadStore(SDNode *N, unsigned IntrID) {
bool IsLoad = IntrID == Intrinsic::amdgcn_tensor_load_to_lds;
- unsigned Opc = IsLoad ? AMDGPU::TENSOR_LOAD_TO_LDS :
- AMDGPU::TENSOR_STORE_FROM_LDS;
+ unsigned Opc =
+ IsLoad ? AMDGPU::TENSOR_LOAD_TO_LDS : AMDGPU::TENSOR_STORE_FROM_LDS;
SmallVector<SDValue, 7> TensorOps;
// First two groups
@@ -3020,9 +3020,9 @@ void AMDGPUDAGToDAGISel::SelectTensorLoadStore(SDNode *N,
unsigned IntrID) {
SDValue Group3 = N->getOperand(5);
if (ISD::isBuildVectorAllZeros(Group2.getNode()) &&
ISD::isBuildVectorAllZeros(Group3.getNode())) {
- Opc = IsLoad ? AMDGPU::TENSOR_LOAD_TO_LDS_D2 :
- AMDGPU::TENSOR_STORE_FROM_LDS_D2;
- } else { // Has at least 4 groups
+ Opc = IsLoad ? AMDGPU::TENSOR_LOAD_TO_LDS_D2
+ : AMDGPU::TENSOR_STORE_FROM_LDS_D2;
+ } else { // Has at least 4 groups
TensorOps.push_back(Group2); // D# group 2
TensorOps.push_back(Group3); // D# group 3
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 14c50a52b..3ae638f14 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -3793,8 +3793,8 @@ bool
AMDGPUInstructionSelector::selectGlobalLoadLds(MachineInstr &MI) const{
bool AMDGPUInstructionSelector::selectTensorLoadStore(MachineInstr &MI,
Intrinsic::ID IID) const
{
bool IsLoad = IID == Intrinsic::amdgcn_tensor_load_to_lds;
- unsigned Opc = IsLoad ? AMDGPU::TENSOR_LOAD_TO_LDS :
- AMDGPU::TENSOR_STORE_FROM_LDS;
+ unsigned Opc =
+ IsLoad ? AMDGPU::TENSOR_LOAD_TO_LDS : AMDGPU::TENSOR_STORE_FROM_LDS;
int NumGroups = 4;
// A lamda function to check whether an operand is a vector of all 0s.
@@ -3808,24 +3808,24 @@ bool
AMDGPUInstructionSelector::selectTensorLoadStore(MachineInstr &MI,
// Use _D2 version if both group 2 and 3 are zero-initialized.
if (isAllZeros(MI.getOperand(3)) && isAllZeros(MI.getOperand(4))) {
NumGroups = 2;
- Opc = IsLoad ? AMDGPU::TENSOR_LOAD_TO_LDS_D2 :
- AMDGPU::TENSOR_STORE_FROM_LDS_D2;
+ Opc = IsLoad ? AMDGPU::TENSOR_LOAD_TO_LDS_D2
+ : AMDGPU::TENSOR_STORE_FROM_LDS_D2;
}
// TODO: Handle the fifth group: MI.getOpetand(5), which is silently ignored
// for now because all existing targets only support up to 4 groups.
MachineBasicBlock *MBB = MI.getParent();
auto MIB = BuildMI(*MBB, &MI, MI.getDebugLoc(), TII.get(Opc))
- .add(MI.getOperand(1)) // D# group 0
- .add(MI.getOperand(2)); // D# group 1
+ .add(MI.getOperand(1)) // D# group 0
+ .add(MI.getOperand(2)); // D# group 1
- if (NumGroups >= 4) { // Has at least 4 groups
- MIB.add(MI.getOperand(3)) // D# group 2
- .add(MI.getOperand(4)); // D# group 3
+ if (NumGroups >= 4) { // Has at least 4 groups
+ MIB.add(MI.getOperand(3)) // D# group 2
+ .add(MI.getOperand(4)); // D# group 3
}
MIB.addImm(0) // r128
- .add(MI.getOperand(6)); // cpol
+ .add(MI.getOperand(6)); // cpol
MI.eraseFromParent();
return true;
``````````
</details>
https://github.com/llvm/llvm-project/pull/182334
_______________________________________________
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
