asavonic wrote: > My concern here is with 1) how the merging happens, and 2) what is intended > to happen when one module has target features or other flags that conflict. > I beleive RISC-V has at least a few. @mshockwave may be able to point you > to some.
By target features you mean `-mcpu` and `-mattr`? (`CPU` and `Features` arguments for `MCSubtargetInfo`) The intent of the patch is to avoid dealing with them at all after Clang and before the final CodeGen, at least for handling of global inline asm. Clang has just one set of features provided in command line. Same for the final CodeGen - users are responsible to provide a "correct" set of features to compile the given IR. Clang does not save features in IR as an attribute of a module (except for RISC-V), therefore there is no problem of merging them when linking two modules. For RISC-V, Clang formats features into a `riscv-isa` module flag with `ModFlagBehavior::AppendUnique`. When modules are linked, `riscv-isa` flags from all modules are collected as a list. RISC-V AsmParser reads this list and decides what features to enable or disable. This mechanism is not used for other targets, and we don't rely on it with this patch. Merging features as module attributes is difficult, because we have to form a non-contradicting set of features every time we merge. Even simple cases like merging a module with `+fp16` and another one with `-fp16` is confusing: `+fp16-fp16` and `-fp16+fp16` are completely different results. Hence why in this patch we remove the requirement on having accurate target features to handle global assembly in IR. All we need from assembly is a symbol table, and merging of symbol tables seems much easier than merging of target features. https://github.com/llvm/llvm-project/pull/174995 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
