Author: Farzon Lotfi Date: 2026-02-22T08:23:17-05:00 New Revision: 844619e52653d084c898131e890e0c2411033e67
URL: https://github.com/llvm/llvm-project/commit/844619e52653d084c898131e890e0c2411033e67 DIFF: https://github.com/llvm/llvm-project/commit/844619e52653d084c898131e890e0c2411033e67.diff LOG: Revert "[HLSL][DXIL][SPRIV] Added WaveActiveProduct intrinsic #164385" (#182741) Reverts llvm/llvm-project#165109 Added: Modified: clang/include/clang/Basic/Builtins.td clang/lib/CodeGen/CGHLSLBuiltins.cpp clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h clang/lib/Sema/SemaHLSL.cpp llvm/include/llvm/IR/IntrinsicsDirectX.td llvm/include/llvm/IR/IntrinsicsSPIRV.td llvm/lib/Target/DirectX/DXIL.td llvm/lib/Target/DirectX/DXILShaderFlags.cpp llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll Removed: clang/test/CodeGenHLSL/builtins/WaveActiveProduct.hlsl clang/test/SemaHLSL/BuiltIns/WaveActiveProduct-errors.hlsl llvm/test/CodeGen/DirectX/WaveActiveProduct.ll llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveProduct.ll ################################################################################ diff --git a/clang/include/clang/Basic/Builtins.td b/clang/include/clang/Basic/Builtins.td index 6880a6e177c00..78dd26aa2c455 100644 --- a/clang/include/clang/Basic/Builtins.td +++ b/clang/include/clang/Basic/Builtins.td @@ -5174,12 +5174,6 @@ def HLSLWaveActiveSum : LangBuiltin<"HLSL_LANG"> { let Prototype = "void (...)"; } -def HLSLWaveActiveProduct : LangBuiltin<"HLSL_LANG"> { - let Spellings = ["__builtin_hlsl_wave_active_product"]; - let Attributes = [NoThrow, Const]; - let Prototype = "void (...)"; -} - def HLSLWaveGetLaneIndex : LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_wave_get_lane_index"]; let Attributes = [NoThrow, Const]; diff --git a/clang/lib/CodeGen/CGHLSLBuiltins.cpp b/clang/lib/CodeGen/CGHLSLBuiltins.cpp index 6cd379fb6ba3d..70891eac39425 100644 --- a/clang/lib/CodeGen/CGHLSLBuiltins.cpp +++ b/clang/lib/CodeGen/CGHLSLBuiltins.cpp @@ -331,7 +331,7 @@ static Intrinsic::ID getFirstBitHighIntrinsic(CGHLSLRuntime &RT, QualType QT) { // Return wave active sum that corresponds to the QT scalar type static Intrinsic::ID getWaveActiveSumIntrinsic(llvm::Triple::ArchType Arch, - QualType QT) { + CGHLSLRuntime &RT, QualType QT) { switch (Arch) { case llvm::Triple::spirv: return Intrinsic::spv_wave_reduce_sum; @@ -346,23 +346,6 @@ static Intrinsic::ID getWaveActiveSumIntrinsic(llvm::Triple::ArchType Arch, } } -// Return wave active product that corresponds to the QT scalar type -static Intrinsic::ID getWaveActiveProductIntrinsic(llvm::Triple::ArchType Arch, - QualType QT) { - switch (Arch) { - case llvm::Triple::spirv: - return Intrinsic::spv_wave_product; - case llvm::Triple::dxil: { - if (QT->isUnsignedIntegerType()) - return Intrinsic::dx_wave_uproduct; - return Intrinsic::dx_wave_product; - } - default: - llvm_unreachable("Intrinsic WaveActiveProduct" - " not supported by target architecture"); - } -} - static Intrinsic::ID getPrefixCountBitsIntrinsic(llvm::Triple::ArchType Arch) { switch (Arch) { case llvm::Triple::spirv: @@ -1138,27 +1121,18 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, ArrayRef{OpExpr}); } case Builtin::BI__builtin_hlsl_wave_active_sum: { - // Due to the use of variadic arguments, explicitly retrieve argument + // Due to the use of variadic arguments, explicitly retreive argument Value *OpExpr = EmitScalarExpr(E->getArg(0)); Intrinsic::ID IID = getWaveActiveSumIntrinsic( - getTarget().getTriple().getArch(), E->getArg(0)->getType()); + getTarget().getTriple().getArch(), CGM.getHLSLRuntime(), + E->getArg(0)->getType()); return EmitRuntimeCall(Intrinsic::getOrInsertDeclaration( &CGM.getModule(), IID, {OpExpr->getType()}), ArrayRef{OpExpr}, "hlsl.wave.active.sum"); } - case Builtin::BI__builtin_hlsl_wave_active_product: { - // Due to the use of variadic arguments, explicitly retrieve argument - Value *OpExpr = EmitScalarExpr(E->getArg(0)); - Intrinsic::ID IID = getWaveActiveProductIntrinsic( - getTarget().getTriple().getArch(), E->getArg(0)->getType()); - - return EmitRuntimeCall(Intrinsic::getOrInsertDeclaration( - &CGM.getModule(), IID, {OpExpr->getType()}), - ArrayRef{OpExpr}, "hlsl.wave.active.product"); - } case Builtin::BI__builtin_hlsl_wave_active_max: { - // Due to the use of variadic arguments, explicitly retrieve argument + // Due to the use of variadic arguments, explicitly retreive argument Value *OpExpr = EmitScalarExpr(E->getArg(0)); QualType QT = E->getArg(0)->getType(); Intrinsic::ID IID; @@ -1172,7 +1146,7 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, ArrayRef{OpExpr}, "hlsl.wave.active.max"); } case Builtin::BI__builtin_hlsl_wave_active_min: { - // Due to the use of variadic arguments, explicitly retrieve argument + // Due to the use of variadic arguments, explicitly retreive argument Value *OpExpr = EmitScalarExpr(E->getArg(0)); QualType QT = E->getArg(0)->getType(); Intrinsic::ID IID; @@ -1213,7 +1187,7 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, Intrinsic::getOrInsertDeclaration(&CGM.getModule(), ID)); } case Builtin::BI__builtin_hlsl_wave_read_lane_at: { - // Due to the use of variadic arguments we must explicitly retrieve them and + // Due to the use of variadic arguments we must explicitly retreive them and // create our function type. Value *OpExpr = EmitScalarExpr(E->getArg(0)); Value *OpIndex = EmitScalarExpr(E->getArg(1)); diff --git a/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h b/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h index 979e19cd0035a..2543401bdfbf9 100644 --- a/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h +++ b/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h @@ -2908,129 +2908,6 @@ __attribute__((convergent)) double3 WaveActiveSum(double3); _HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_sum) __attribute__((convergent)) double4 WaveActiveSum(double4); -//===----------------------------------------------------------------------===// -// WaveActiveProduct builtins -//===----------------------------------------------------------------------===// - -_HLSL_16BIT_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) half WaveActiveProduct(half); -_HLSL_16BIT_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) half2 WaveActiveProduct(half2); -_HLSL_16BIT_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) half3 WaveActiveProduct(half3); -_HLSL_16BIT_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) half4 WaveActiveProduct(half4); - -#ifdef __HLSL_ENABLE_16_BIT -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) int16_t WaveActiveProduct(int16_t); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) int16_t2 WaveActiveProduct(int16_t2); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) int16_t3 WaveActiveProduct(int16_t3); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) int16_t4 WaveActiveProduct(int16_t4); - -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) uint16_t WaveActiveProduct(uint16_t); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) uint16_t2 WaveActiveProduct(uint16_t2); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) uint16_t3 WaveActiveProduct(uint16_t3); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) uint16_t4 WaveActiveProduct(uint16_t4); -#endif - -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) int WaveActiveProduct(int); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) int2 WaveActiveProduct(int2); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) int3 WaveActiveProduct(int3); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) int4 WaveActiveProduct(int4); - -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) uint WaveActiveProduct(uint); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) uint2 WaveActiveProduct(uint2); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) uint3 WaveActiveProduct(uint3); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) uint4 WaveActiveProduct(uint4); - -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) int64_t WaveActiveProduct(int64_t); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) int64_t2 WaveActiveProduct(int64_t2); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) int64_t3 WaveActiveProduct(int64_t3); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) int64_t4 WaveActiveProduct(int64_t4); - -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) uint64_t WaveActiveProduct(uint64_t); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) uint64_t2 WaveActiveProduct(uint64_t2); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) uint64_t3 WaveActiveProduct(uint64_t3); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) uint64_t4 WaveActiveProduct(uint64_t4); - -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) float WaveActiveProduct(float); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) float2 WaveActiveProduct(float2); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) float3 WaveActiveProduct(float3); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) float4 WaveActiveProduct(float4); - -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) double WaveActiveProduct(double); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) double2 WaveActiveProduct(double2); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) double3 WaveActiveProduct(double3); -_HLSL_AVAILABILITY(shadermodel, 6.0) -_HLSL_BUILTIN_ALIAS(__builtin_hlsl_wave_active_product) -__attribute__((convergent)) double4 WaveActiveProduct(double4); - //===----------------------------------------------------------------------===// // WavePrefixSum builtins //===----------------------------------------------------------------------===// diff --git a/clang/lib/Sema/SemaHLSL.cpp b/clang/lib/Sema/SemaHLSL.cpp index f802b9ae7e420..911dba40d3bde 100644 --- a/clang/lib/Sema/SemaHLSL.cpp +++ b/clang/lib/Sema/SemaHLSL.cpp @@ -3811,8 +3811,7 @@ bool SemaHLSL::CheckBuiltinFunctionCall(unsigned BuiltinID, CallExpr *TheCall) { } case Builtin::BI__builtin_hlsl_wave_active_max: case Builtin::BI__builtin_hlsl_wave_active_min: - case Builtin::BI__builtin_hlsl_wave_active_sum: - case Builtin::BI__builtin_hlsl_wave_active_product: { + case Builtin::BI__builtin_hlsl_wave_active_sum: { if (SemaRef.checkArgCount(TheCall, 1)) return true; diff --git a/clang/test/CodeGenHLSL/builtins/WaveActiveProduct.hlsl b/clang/test/CodeGenHLSL/builtins/WaveActiveProduct.hlsl deleted file mode 100644 index 3a8320e7333fc..0000000000000 --- a/clang/test/CodeGenHLSL/builtins/WaveActiveProduct.hlsl +++ /dev/null @@ -1,45 +0,0 @@ -// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \ -// RUN: dxil-pc-shadermodel6.3-compute %s -emit-llvm -disable-llvm-passes -o - | \ -// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-DXIL -// RUN: %clang_cc1 -std=hlsl2021 -finclude-default-header -triple \ -// RUN: spirv-pc-vulkan-compute %s -emit-llvm -disable-llvm-passes -o - | \ -// RUN: FileCheck %s --check-prefixes=CHECK,CHECK-SPIRV - -// Test basic lowering to runtime function call. - -// CHECK-LABEL: test_int -int test_int(int expr) { - // CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.product.i32([[TY]] %[[#]]) - // CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.product.i32([[TY]] %[[#]]) - // CHECK: ret [[TY]] %[[RET]] - return WaveActiveProduct(expr); -} - -// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.product.i32([[TY]]) #[[#attr:]] -// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.product.i32([[TY]]) #[[#attr:]] - -// CHECK-LABEL: test_uint64_t -uint64_t test_uint64_t(uint64_t expr) { - // CHECK-SPIRV: %[[RET:.*]] = call spir_func [[TY:.*]] @llvm.spv.wave.product.i64([[TY]] %[[#]]) - // CHECK-DXIL: %[[RET:.*]] = call [[TY:.*]] @llvm.dx.wave.uproduct.i64([[TY]] %[[#]]) - // CHECK: ret [[TY]] %[[RET]] - return WaveActiveProduct(expr); -} - -// CHECK-DXIL: declare [[TY]] @llvm.dx.wave.uproduct.i64([[TY]]) #[[#attr:]] -// CHECK-SPIRV: declare [[TY]] @llvm.spv.wave.product.i64([[TY]]) #[[#attr:]] - -// Test basic lowering to runtime function call with array and float value. - -// CHECK-LABEL: test_floatv4 -float4 test_floatv4(float4 expr) { - // CHECK-SPIRV: %[[RET1:.*]] = call reassoc nnan ninf nsz arcp afn spir_func [[TY1:.*]] @llvm.spv.wave.product.v4f32([[TY1]] %[[#]] - // CHECK-DXIL: %[[RET1:.*]] = call reassoc nnan ninf nsz arcp afn [[TY1:.*]] @llvm.dx.wave.product.v4f32([[TY1]] %[[#]]) - // CHECK: ret [[TY1]] %[[RET1]] - return WaveActiveProduct(expr); -} - -// CHECK-DXIL: declare [[TY1]] @llvm.dx.wave.product.v4f32([[TY1]]) #[[#attr]] -// CHECK-SPIRV: declare [[TY1]] @llvm.spv.wave.product.v4f32([[TY1]]) #[[#attr]] - -// CHECK: attributes #[[#attr]] = {{{.*}} convergent {{.*}}} diff --git a/clang/test/SemaHLSL/BuiltIns/WaveActiveProduct-errors.hlsl b/clang/test/SemaHLSL/BuiltIns/WaveActiveProduct-errors.hlsl deleted file mode 100644 index 43ad02b35fc1c..0000000000000 --- a/clang/test/SemaHLSL/BuiltIns/WaveActiveProduct-errors.hlsl +++ /dev/null @@ -1,28 +0,0 @@ -// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -emit-llvm-only -disable-llvm-passes -verify - -int test_too_few_arg() { - return __builtin_hlsl_wave_active_product(); - // expected-error@-1 {{too few arguments to function call, expected 1, have 0}} -} - -float2 test_too_many_arg(float2 p0) { - return __builtin_hlsl_wave_active_product(p0, p0); - // expected-error@-1 {{too many arguments to function call, expected 1, have 2}} -} - -bool test_expr_bool_type_check(bool p0) { - return __builtin_hlsl_wave_active_product(p0); - // expected-error@-1 {{invalid operand of type 'bool'}} -} - -bool2 test_expr_bool_vec_type_check(bool2 p0) { - return __builtin_hlsl_wave_active_product(p0); - // expected-error@-1 {{invalid operand of type 'bool2' (aka 'vector<bool, 2>')}} -} - -struct S { float f; }; - -S test_expr_struct_type_check(S p0) { - return __builtin_hlsl_wave_active_product(p0); - // expected-error@-1 {{invalid operand of type 'S' where a scalar or vector is required}} -} diff --git a/llvm/include/llvm/IR/IntrinsicsDirectX.td b/llvm/include/llvm/IR/IntrinsicsDirectX.td index 7caf839c3a50b..909482d72aa88 100644 --- a/llvm/include/llvm/IR/IntrinsicsDirectX.td +++ b/llvm/include/llvm/IR/IntrinsicsDirectX.td @@ -223,8 +223,6 @@ def int_dx_wave_reduce_min : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType def int_dx_wave_reduce_umin : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_dx_wave_reduce_sum : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_dx_wave_reduce_usum : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; -def int_dx_wave_product : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; -def int_dx_wave_uproduct : DefaultAttrsIntrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_dx_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>; def int_dx_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>; def int_dx_wave_get_lane_count diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td index f9f587f647078..77f49ae721ad5 100644 --- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td +++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td @@ -129,7 +129,6 @@ def int_spv_rsqrt : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty] def int_spv_wave_reduce_min : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_spv_wave_reduce_umin : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_spv_wave_reduce_sum : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; - def int_spv_wave_product : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_spv_wave_is_first_lane : DefaultAttrsIntrinsic<[llvm_i1_ty], [], [IntrConvergent]>; def int_spv_wave_readlane : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrConvergent, IntrNoMem]>; def int_spv_wave_get_lane_count diff --git a/llvm/lib/Target/DirectX/DXIL.td b/llvm/lib/Target/DirectX/DXIL.td index 8cdfea3cb80c8..59a5b7fe4d508 100644 --- a/llvm/lib/Target/DirectX/DXIL.td +++ b/llvm/lib/Target/DirectX/DXIL.td @@ -1093,16 +1093,6 @@ def WaveActiveOp : DXILOp<119, waveActiveOp> { IntrinArgIndex<0>, IntrinArgI8<WaveOpKind_Sum>, IntrinArgI8<SignedOpKind_Unsigned> ]>, - IntrinSelect<int_dx_wave_product, - [ - IntrinArgIndex<0>, IntrinArgI8<WaveOpKind_Product>, - IntrinArgI8<SignedOpKind_Signed> - ]>, - IntrinSelect<int_dx_wave_uproduct, - [ - IntrinArgIndex<0>, IntrinArgI8<WaveOpKind_Product>, - IntrinArgI8<SignedOpKind_Unsigned> - ]>, IntrinSelect<int_dx_wave_reduce_max, [ IntrinArgIndex<0>, IntrinArgI8<WaveOpKind_Max>, diff --git a/llvm/lib/Target/DirectX/DXILShaderFlags.cpp b/llvm/lib/Target/DirectX/DXILShaderFlags.cpp index 77ba95dfb0fe3..52993ee1c1220 100644 --- a/llvm/lib/Target/DirectX/DXILShaderFlags.cpp +++ b/llvm/lib/Target/DirectX/DXILShaderFlags.cpp @@ -93,8 +93,6 @@ static bool checkWaveOps(Intrinsic::ID IID) { // Wave Active Op Variants case Intrinsic::dx_wave_reduce_sum: case Intrinsic::dx_wave_reduce_usum: - case Intrinsic::dx_wave_product: - case Intrinsic::dx_wave_uproduct: case Intrinsic::dx_wave_reduce_max: case Intrinsic::dx_wave_reduce_umax: case Intrinsic::dx_wave_reduce_min: diff --git a/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp b/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp index 3c5bc471acd7f..8018b09c9f248 100644 --- a/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp +++ b/llvm/lib/Target/DirectX/DirectXTargetTransformInfo.cpp @@ -61,13 +61,11 @@ bool DirectXTTIImpl::isTargetIntrinsicTriviallyScalarizable( case Intrinsic::dx_wave_reduce_max: case Intrinsic::dx_wave_reduce_min: case Intrinsic::dx_wave_reduce_sum: - case Intrinsic::dx_wave_product: case Intrinsic::dx_wave_prefix_sum: case Intrinsic::dx_wave_prefix_product: case Intrinsic::dx_wave_reduce_umax: case Intrinsic::dx_wave_reduce_umin: case Intrinsic::dx_wave_reduce_usum: - case Intrinsic::dx_wave_uproduct: case Intrinsic::dx_wave_prefix_usum: case Intrinsic::dx_wave_prefix_uproduct: case Intrinsic::dx_imad: diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index a8e1e7064aaca..3d3e311eeedb7 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -250,9 +250,6 @@ class SPIRVInstructionSelector : public InstructionSelector { bool selectWaveReduceSum(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const; - bool selectWaveReduceProduct(Register ResVReg, const SPIRVType *ResType, - MachineInstr &I) const; - template <typename PickOpcodeFn> bool selectWaveExclusiveScan(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I, bool IsUnsigned, @@ -1904,15 +1901,15 @@ bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg, ValueReg = TmpReg; } - BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(NewOpcode)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(Ptr) - .addUse(ScopeReg) - .addUse(MemSemReg) - .addUse(ValueReg) - .constrainAllUses(TII, TRI, RBI); - return true; + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(NewOpcode)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(Ptr) + .addUse(ScopeReg) + .addUse(MemSemReg) + .addUse(ValueReg) + .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectUnmergeValues(MachineInstr &I) const { @@ -2562,12 +2559,12 @@ bool SPIRVInstructionSelector::selectIntegerDotExpansion( for (unsigned i = 1; i < GR.getScalarOrVectorComponentCount(VecType); i++) { Register Elt = MRI->createVirtualRegister(GR.getRegClass(ResType)); - BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) - .addDef(Elt) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(TmpVec) - .addImm(i) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) + .addDef(Elt) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(TmpVec) + .addImm(i) + .constrainAllUses(TII, TRI, RBI); Register Sum = i < GR.getScalarOrVectorComponentCount(VecType) - 1 ? MRI->createVirtualRegister(GR.getRegClass(ResType)) @@ -2768,13 +2765,13 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg, ? MRI->createVirtualRegister(&SPIRV::IDRegClass) : ResVReg; - BuildMI(BB, I, DL, TII.get(SPIRV::OpExtInst)) - .addDef(SignReg) - .addUse(GR.getSPIRVTypeID(InputType)) - .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450)) - .addImm(SignOpcode) - .addUse(InputRegister) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, DL, TII.get(SPIRV::OpExtInst)) + .addDef(SignReg) + .addUse(GR.getSPIRVTypeID(InputType)) + .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450)) + .addImm(SignOpcode) + .addUse(InputRegister) + .constrainAllUses(TII, TRI, RBI); if (NeedsConversion) { auto ConvertOpcode = IsFloatTy ? SPIRV::OpConvertFToS : SPIRV::OpSConvert; @@ -2926,18 +2923,6 @@ bool SPIRVInstructionSelector::selectWaveReduceSum(Register ResVReg, }); } -bool SPIRVInstructionSelector::selectWaveReduceProduct(Register ResVReg, - const SPIRVType *ResType, - MachineInstr &I) const { - return selectWaveReduce(ResVReg, ResType, I, /*IsUnsigned*/ false, - [&](Register InputRegister, bool IsUnsigned) { - bool IsFloatTy = GR.isScalarOrVectorOfType( - InputRegister, SPIRV::OpTypeFloat); - return IsFloatTy ? SPIRV::OpGroupNonUniformFMul - : SPIRV::OpGroupNonUniformIMul; - }); -} - template <typename PickOpcodeFn> bool SPIRVInstructionSelector::selectWaveReduce( Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I, bool IsUnsigned, @@ -3734,22 +3719,22 @@ bool SPIRVInstructionSelector::selectDerivativeInst( Register ConvertToVReg = MRI->createVirtualRegister(RegClass); Register DpdOpVReg = MRI->createVirtualRegister(RegClass); - BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert)) - .addDef(ConvertToVReg) - .addUse(GR.getSPIRVTypeID(F32ConvertTy)) - .addUse(SrcReg) - .constrainAllUses(TII, TRI, RBI); - BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DPdOpCode)) - .addDef(DpdOpVReg) - .addUse(GR.getSPIRVTypeID(F32ConvertTy)) - .addUse(ConvertToVReg) - .constrainAllUses(TII, TRI, RBI); - BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(DpdOpVReg) - .constrainAllUses(TII, TRI, RBI); - return true; + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert)) + .addDef(ConvertToVReg) + .addUse(GR.getSPIRVTypeID(F32ConvertTy)) + .addUse(SrcReg) + .constrainAllUses(TII, TRI, RBI); + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DPdOpCode)) + .addDef(DpdOpVReg) + .addUse(GR.getSPIRVTypeID(F32ConvertTy)) + .addUse(ConvertToVReg) + .constrainAllUses(TII, TRI, RBI); + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(DpdOpVReg) + .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, @@ -4118,8 +4103,6 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, return selectWaveReduceMin(ResVReg, ResType, I, /*IsUnsigned*/ false); case Intrinsic::spv_wave_reduce_sum: return selectWaveReduceSum(ResVReg, ResType, I); - case Intrinsic::spv_wave_product: - return selectWaveReduceProduct(ResVReg, ResType, I); case Intrinsic::spv_wave_readlane: return selectWaveOpInst(ResVReg, ResType, I, SPIRV::OpGroupNonUniformShuffle); diff --git a/llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll b/llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll index 0ce0cfffc9ac9..be53d19aca8f2 100644 --- a/llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll +++ b/llvm/test/CodeGen/DirectX/ShaderFlags/wave-ops.ll @@ -63,20 +63,6 @@ entry: ret i32 %ret } -define noundef i32 @wave_product(i32 noundef %x) { -entry: - ; CHECK: Function wave_product : [[WAVE_FLAG]] - %ret = call i32 @llvm.dx.wave.product.i32(i32 %x) - ret i32 %ret -} - -define noundef i32 @wave_reduce_uproduct(i32 noundef %x) { -entry: - ; CHECK: Function wave_reduce_uproduct : [[WAVE_FLAG]] - %ret = call i32 @llvm.dx.wave.product.i32(i32 %x) - ret i32 %ret -} - define noundef i32 @wave_reduce_max(i32 noundef %x) { entry: ; CHECK: Function wave_reduce_max : [[WAVE_FLAG]] diff --git a/llvm/test/CodeGen/DirectX/WaveActiveProduct.ll b/llvm/test/CodeGen/DirectX/WaveActiveProduct.ll deleted file mode 100644 index be280e5cd8682..0000000000000 --- a/llvm/test/CodeGen/DirectX/WaveActiveProduct.ll +++ /dev/null @@ -1,143 +0,0 @@ -; RUN: opt -S -scalarizer -dxil-op-lower -mtriple=dxil-pc-shadermodel6.3-library < %s | FileCheck %s - -; Test that for scalar values, WaveAcitveProduct maps down to the DirectX op - -define noundef half @wave_active_product_half(half noundef %expr) { -entry: -; CHECK: call half @dx.op.waveActiveOp.f16(i32 119, half %expr, i8 1, i8 0) - %ret = call half @llvm.dx.wave.product.f16(half %expr) - ret half %ret -} - -define noundef float @wave_active_product_float(float noundef %expr) { -entry: -; CHECK: call float @dx.op.waveActiveOp.f32(i32 119, float %expr, i8 1, i8 0) - %ret = call float @llvm.dx.wave.product.f32(float %expr) - ret float %ret -} - -define noundef double @wave_active_product_double(double noundef %expr) { -entry: -; CHECK: call double @dx.op.waveActiveOp.f64(i32 119, double %expr, i8 1, i8 0) - %ret = call double @llvm.dx.wave.product.f64(double %expr) - ret double %ret -} - -define noundef i16 @wave_active_product_i16(i16 noundef %expr) { -entry: -; CHECK: call i16 @dx.op.waveActiveOp.i16(i32 119, i16 %expr, i8 1, i8 0) - %ret = call i16 @llvm.dx.wave.product.i16(i16 %expr) - ret i16 %ret -} - -define noundef i32 @wave_active_product_i32(i32 noundef %expr) { -entry: -; CHECK: call i32 @dx.op.waveActiveOp.i32(i32 119, i32 %expr, i8 1, i8 0) - %ret = call i32 @llvm.dx.wave.product.i32(i32 %expr) - ret i32 %ret -} - -define noundef i64 @wave_active_product_i64(i64 noundef %expr) { -entry: -; CHECK: call i64 @dx.op.waveActiveOp.i64(i32 119, i64 %expr, i8 1, i8 0) - %ret = call i64 @llvm.dx.wave.product.i64(i64 %expr) - ret i64 %ret -} - -define noundef i16 @wave_active_uproduct_i16(i16 noundef %expr) { -entry: -; CHECK: call i16 @dx.op.waveActiveOp.i16(i32 119, i16 %expr, i8 1, i8 1) - %ret = call i16 @llvm.dx.wave.uproduct.i16(i16 %expr) - ret i16 %ret -} - -define noundef i32 @wave_active_uproduct_i32(i32 noundef %expr) { -entry: -; CHECK: call i32 @dx.op.waveActiveOp.i32(i32 119, i32 %expr, i8 1, i8 1) - %ret = call i32 @llvm.dx.wave.uproduct.i32(i32 %expr) - ret i32 %ret -} - -define noundef i64 @wave_active_uproduct_i64(i64 noundef %expr) { -entry: -; CHECK: call i64 @dx.op.waveActiveOp.i64(i32 119, i64 %expr, i8 1, i8 1) - %ret = call i64 @llvm.dx.wave.uproduct.i64(i64 %expr) - ret i64 %ret -} - -declare half @llvm.dx.wave.product.f16(half) -declare float @llvm.dx.wave.product.f32(float) -declare double @llvm.dx.wave.product.f64(double) - -declare i16 @llvm.dx.wave.product.i16(i16) -declare i32 @llvm.dx.wave.product.i32(i32) -declare i64 @llvm.dx.wave.product.i64(i64) - -declare i16 @llvm.dx.wave.uproduct.i16(i16) -declare i32 @llvm.dx.wave.uproduct.i32(i32) -declare i64 @llvm.dx.wave.uproduct.i64(i64) - -; Test that for vector values, WaveAcitveProduct scalarizes and maps down to the -; DirectX op - -define noundef <2 x half> @wave_active_product_v2half(<2 x half> noundef %expr) { -entry: -; CHECK: call half @dx.op.waveActiveOp.f16(i32 119, half %expr.i0, i8 1, i8 0) -; CHECK: call half @dx.op.waveActiveOp.f16(i32 119, half %expr.i1, i8 1, i8 0) - %ret = call <2 x half> @llvm.dx.wave.product.v2f16(<2 x half> %expr) - ret <2 x half> %ret -} - -define noundef <3 x i32> @wave_active_product_v3i32(<3 x i32> noundef %expr) { -entry: -; CHECK: call i32 @dx.op.waveActiveOp.i32(i32 119, i32 %expr.i0, i8 1, i8 0) -; CHECK: call i32 @dx.op.waveActiveOp.i32(i32 119, i32 %expr.i1, i8 1, i8 0) -; CHECK: call i32 @dx.op.waveActiveOp.i32(i32 119, i32 %expr.i2, i8 1, i8 0) - %ret = call <3 x i32> @llvm.dx.wave.product.v3i32(<3 x i32> %expr) - ret <3 x i32> %ret -} - -define noundef <4 x double> @wave_active_product_v4f64(<4 x double> noundef %expr) { -entry: -; CHECK: call double @dx.op.waveActiveOp.f64(i32 119, double %expr.i0, i8 1, i8 0) -; CHECK: call double @dx.op.waveActiveOp.f64(i32 119, double %expr.i1, i8 1, i8 0) -; CHECK: call double @dx.op.waveActiveOp.f64(i32 119, double %expr.i2, i8 1, i8 0) -; CHECK: call double @dx.op.waveActiveOp.f64(i32 119, double %expr.i3, i8 1, i8 0) - %ret = call <4 x double> @llvm.dx.wave.product.v464(<4 x double> %expr) - ret <4 x double> %ret -} - -declare <2 x half> @llvm.dx.wave.product.v2f16(<2 x half>) -declare <3 x i32> @llvm.dx.wave.product.v3i32(<3 x i32>) -declare <4 x double> @llvm.dx.wave.product.v4f64(<4 x double>) - -define noundef <2 x i16> @wave_active_uproduct_v2i16(<2 x i16> noundef %expr) { -entry: -; CHECK: call i16 @dx.op.waveActiveOp.i16(i32 119, i16 %expr.i0, i8 1, i8 1) -; CHECK: call i16 @dx.op.waveActiveOp.i16(i32 119, i16 %expr.i1, i8 1, i8 1) - %ret = call <2 x i16> @llvm.dx.wave.uproduct.v2f16(<2 x i16> %expr) - ret <2 x i16> %ret -} - -define noundef <3 x i32> @wave_active_uproduct_v3i32(<3 x i32> noundef %expr) { -entry: -; CHECK: call i32 @dx.op.waveActiveOp.i32(i32 119, i32 %expr.i0, i8 1, i8 1) -; CHECK: call i32 @dx.op.waveActiveOp.i32(i32 119, i32 %expr.i1, i8 1, i8 1) -; CHECK: call i32 @dx.op.waveActiveOp.i32(i32 119, i32 %expr.i2, i8 1, i8 1) - %ret = call <3 x i32> @llvm.dx.wave.uproduct.v3i32(<3 x i32> %expr) - ret <3 x i32> %ret -} - -define noundef <4 x i64> @wave_active_uproduct_v4f64(<4 x i64> noundef %expr) { -entry: -; CHECK: call i64 @dx.op.waveActiveOp.i64(i32 119, i64 %expr.i0, i8 1, i8 1) -; CHECK: call i64 @dx.op.waveActiveOp.i64(i32 119, i64 %expr.i1, i8 1, i8 1) -; CHECK: call i64 @dx.op.waveActiveOp.i64(i32 119, i64 %expr.i2, i8 1, i8 1) -; CHECK: call i64 @dx.op.waveActiveOp.i64(i32 119, i64 %expr.i3, i8 1, i8 1) - %ret = call <4 x i64> @llvm.dx.wave.uproduct.v464(<4 x i64> %expr) - ret <4 x i64> %ret -} - -declare <2 x i16> @llvm.dx.wave.uproduct.v2f16(<2 x i16>) -declare <3 x i32> @llvm.dx.wave.uproduct.v3i32(<3 x i32>) -declare <4 x i64> @llvm.dx.wave.uproduct.v4f64(<4 x i64>) diff --git a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveProduct.ll b/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveProduct.ll deleted file mode 100644 index 1e244dcdb3866..0000000000000 --- a/llvm/test/CodeGen/SPIRV/hlsl-intrinsics/WaveActiveProduct.ll +++ /dev/null @@ -1,41 +0,0 @@ -; RUN: llc -verify-machineinstrs -O0 -mtriple=spirv-vulkan-unknown %s -o - | FileCheck %s -; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv-vulkan-unknown %s -o - -filetype=obj | spirv-val %} - -; Test lowering to spir-v backend for various types and scalar/vector - -; CHECK-DAG: %[[#f16:]] = OpTypeFloat 16 -; CHECK-DAG: %[[#f32:]] = OpTypeFloat 32 -; CHECK-DAG: %[[#uint:]] = OpTypeInt 32 0 -; CHECK-DAG: %[[#v4_half:]] = OpTypeVector %[[#f16]] 4 -; CHECK-DAG: %[[#scope:]] = OpConstant %[[#uint]] 3 - -; CHECK-LABEL: Begin function test_float -; CHECK: %[[#fexpr:]] = OpFunctionParameter %[[#f32]] -define float @test_float(float %fexpr) { -entry: -; CHECK: %[[#fret:]] = OpGroupNonUniformFMul %[[#f32]] %[[#scope]] Reduce %[[#fexpr]] - %0 = call float @llvm.spv.wave.product.f32(float %fexpr) - ret float %0 -} - -; CHECK-LABEL: Begin function test_int -; CHECK: %[[#iexpr:]] = OpFunctionParameter %[[#uint]] -define i32 @test_int(i32 %iexpr) { -entry: -; CHECK: %[[#iret:]] = OpGroupNonUniformIMul %[[#uint]] %[[#scope]] Reduce %[[#iexpr]] - %0 = call i32 @llvm.spv.wave.product.i32(i32 %iexpr) - ret i32 %0 -} - -; CHECK-LABEL: Begin function test_vhalf -; CHECK: %[[#vbexpr:]] = OpFunctionParameter %[[#v4_half]] -define <4 x half> @test_vhalf(<4 x half> %vbexpr) { -entry: -; CHECK: %[[#vhalfret:]] = OpGroupNonUniformFMul %[[#v4_half]] %[[#scope]] Reduce %[[#vbexpr]] - %0 = call <4 x half> @llvm.spv.wave.product.v4half(<4 x half> %vbexpr) - ret <4 x half> %0 -} - -declare float @llvm.spv.wave.product.f32(float) -declare i32 @llvm.spv.wave.product.i32(i32) -declare <4 x half> @llvm.spv.wave.product.v4half(<4 x half>) _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
