================
@@ -17741,6 +17741,53 @@ void AArch64TargetLowering::getTgtMemIntrinsic(
Infos.push_back(Info);
return;
}
+ case Intrinsic::aarch64_stshh_atomic_store: {
+ const auto *OrderC = dyn_cast<ConstantInt>(I.getArgOperand(2));
+ const auto *SizeC = dyn_cast<ConstantInt>(I.getArgOperand(4));
+ if (!OrderC || !SizeC)
+ return;
+
+ unsigned SizeBits = SizeC->getZExtValue();
----------------
CarolineConcatto wrote:
Do we need the checks here? This is a llvm-ir that will probably not accept
anything that is different then the type sizes allowed
https://github.com/llvm/llvm-project/pull/181386
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