================
@@ -17779,6 +17779,40 @@ void AArch64TargetLowering::getTgtMemIntrinsic(
Infos.push_back(Info);
return;
}
+ case Intrinsic::aarch64_stshh_atomic_store: {
+ const auto *OrderC = dyn_cast<ConstantInt>(I.getArgOperand(2));
----------------
CarolineConcatto wrote:
Sorry, I was asking about the code in
[llvm/lib/Target/AArch64/AArch64ISelLowering.cpp](https://github.com/llvm/llvm-project/pull/181386/files#diff-6291e4657dea1f4fecdcb9dc96bfb014f79d4c617f080b2f033943e52732cf69)
I am not sure we need this code once we are using PSEUDO Instructions.
When I look the the other intrinsics it does not look like they are using
pseudo, they are all lowering in ISEL Lowering. So I would like to know if we
need to update this Info in ISel lowering or not.
https://github.com/llvm/llvm-project/pull/181386
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