llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-backend-directx Author: Sietze Riemersma (KungFuDonkey) <details> <summary>Changes</summary> --- Patch is 25.19 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/185383.diff 13 Files Affected: - (modified) clang/include/clang/Basic/Builtins.td (+6) - (modified) clang/lib/CodeGen/CGHLSLBuiltins.cpp (+5) - (modified) clang/lib/CodeGen/CGHLSLRuntime.h (+1) - (modified) clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h (+11) - (added) clang/test/CodeGenHLSL/builtins/GroupMemoryBarrier.hlsl (+20) - (added) clang/test/SemaHLSL/BuiltIns/GroupMemoryBarrier-errors.hlsl (+6) - (modified) llvm/include/llvm/IR/IntrinsicsDirectX.td (+3) - (modified) llvm/include/llvm/IR/IntrinsicsSPIRV.td (+1) - (modified) llvm/lib/Target/DirectX/DXIL.td (+2) - (modified) llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp (+99-83) - (added) llvm/test/CodeGen/DirectX/group_memory_barrier.ll (+8) - (modified) llvm/test/CodeGen/DirectX/group_memory_barrier_with_group_sync.ll (+1-1) - (added) llvm/test/CodeGen/SPIRV/hlsl-intrinsics/group_memory_barrier.ll (+14) ``````````diff diff --git a/clang/include/clang/Basic/Builtins.td b/clang/include/clang/Basic/Builtins.td index 4981711fe786d..10b2e930792c7 100644 --- a/clang/include/clang/Basic/Builtins.td +++ b/clang/include/clang/Basic/Builtins.td @@ -5402,6 +5402,12 @@ def HLSLClip: LangBuiltin<"HLSL_LANG"> { let Prototype = "void(...)"; } +def HLSLGroupMemoryBarrier : LangBuiltin<"HLSL_LANG"> { + let Spellings = ["__builtin_hlsl_group_memory_barrier"]; + let Attributes = [NoThrow, Const]; + let Prototype = "void()"; +} + def HLSLGroupMemoryBarrierWithGroupSync: LangBuiltin<"HLSL_LANG"> { let Spellings = ["__builtin_hlsl_group_memory_barrier_with_group_sync"]; let Attributes = [NoThrow, Const]; diff --git a/clang/lib/CodeGen/CGHLSLBuiltins.cpp b/clang/lib/CodeGen/CGHLSLBuiltins.cpp index 177787d2a9630..ae7325384f9f8 100644 --- a/clang/lib/CodeGen/CGHLSLBuiltins.cpp +++ b/clang/lib/CodeGen/CGHLSLBuiltins.cpp @@ -1355,6 +1355,11 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID, assert(E->getArg(0)->getType()->hasFloatingRepresentation() && "clip operands types mismatch"); return handleHlslClip(E, this); + case Builtin::BI__builtin_hlsl_group_memory_barrier: { + Intrinsic::ID ID = CGM.getHLSLRuntime().getGroupMemoryBarrierIntrinsic(); + return EmitRuntimeCall( + Intrinsic::getOrInsertDeclaration(&CGM.getModule(), ID)); + } case Builtin::BI__builtin_hlsl_group_memory_barrier_with_group_sync: { Intrinsic::ID ID = CGM.getHLSLRuntime().getGroupMemoryBarrierWithGroupSyncIntrinsic(); diff --git a/clang/lib/CodeGen/CGHLSLRuntime.h b/clang/lib/CodeGen/CGHLSLRuntime.h index 466c809fdef78..548ed776d12bd 100644 --- a/clang/lib/CodeGen/CGHLSLRuntime.h +++ b/clang/lib/CodeGen/CGHLSLRuntime.h @@ -184,6 +184,7 @@ class CGHLSLRuntime { GENERATE_HLSL_INTRINSIC_FUNCTION(NonUniformResourceIndex, resource_nonuniformindex) GENERATE_HLSL_INTRINSIC_FUNCTION(BufferUpdateCounter, resource_updatecounter) + GENERATE_HLSL_INTRINSIC_FUNCTION(GroupMemoryBarrier, group_memory_barrier) GENERATE_HLSL_INTRINSIC_FUNCTION(GroupMemoryBarrierWithGroupSync, group_memory_barrier_with_group_sync) GENERATE_HLSL_INTRINSIC_FUNCTION(GetDimensionsX, resource_getdimensions_x) diff --git a/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h b/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h index 7b6160091aece..f12b62df4733c 100644 --- a/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h +++ b/clang/lib/Headers/hlsl/hlsl_alias_intrinsics.h @@ -3411,6 +3411,17 @@ float3 radians(float3); _HLSL_BUILTIN_ALIAS(__builtin_hlsl_elementwise_radians) float4 radians(float4); +//===----------------------------------------------------------------------===// +// GroupMemoryBarrierbuiltins +//===----------------------------------------------------------------------===// + +/// \fn void GroupMemoryBarrier(void) +/// \brief Blocks execution of all threads in a group until all group shared +/// accesses have been completed. + +_HLSL_BUILTIN_ALIAS(__builtin_hlsl_group_memory_barrier) +__attribute__((convergent)) void GroupMemoryBarrier(void); + //===----------------------------------------------------------------------===// // GroupMemoryBarrierWithGroupSync builtins //===----------------------------------------------------------------------===// diff --git a/clang/test/CodeGenHLSL/builtins/GroupMemoryBarrier.hlsl b/clang/test/CodeGenHLSL/builtins/GroupMemoryBarrier.hlsl new file mode 100644 index 0000000000000..b52819973f677 --- /dev/null +++ b/clang/test/CodeGenHLSL/builtins/GroupMemoryBarrier.hlsl @@ -0,0 +1,20 @@ +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \ +// RUN: dxil-pc-shadermodel6.3-library %s \ +// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \ +// RUN: -DTARGET=dx -check-prefixes=CHECK,CHECK-DXIL +// RUN: %clang_cc1 -finclude-default-header -x hlsl -triple \ +// RUN: spirv-unknown-vulkan-compute %s \ +// RUN: -emit-llvm -disable-llvm-passes -o - | FileCheck %s \ +// RUN: -DTARGET=spv -check-prefixes=CHECK,CHECK-SPIRV + +// CHECK-DXIL: define hidden void @ +// CHECK-SPIRV: define hidden spir_func void @ +void test_GroupMemoryBarrier() { +// CHECK-DXIL: call void @llvm.[[TARGET]].group.memory.barrier() +// CHECK-SPIRV: call spir_func void @llvm.[[TARGET]].group.memory.barrier() + GroupMemoryBarrier(); +} + +// CHECK: declare void @llvm.[[TARGET]].group.memory.barrier() #[[ATTRS:[0-9]+]] +// CHECK-NOT: attributes #[[ATTRS]] = {{.+}}memory(none){{.+}} +// CHECK: attributes #[[ATTRS]] = {{.+}}convergent{{.+}} diff --git a/clang/test/SemaHLSL/BuiltIns/GroupMemoryBarrier-errors.hlsl b/clang/test/SemaHLSL/BuiltIns/GroupMemoryBarrier-errors.hlsl new file mode 100644 index 0000000000000..5c5761c31eb90 --- /dev/null +++ b/clang/test/SemaHLSL/BuiltIns/GroupMemoryBarrier-errors.hlsl @@ -0,0 +1,6 @@ +// RUN: %clang_cc1 -finclude-default-header -triple dxil-pc-shadermodel6.6-library %s -emit-llvm-only -disable-llvm-passes -verify + +void test_too_many_arg() { + __builtin_hlsl_group_memory_barrier(0); + // expected-error@-1 {{too many arguments to function call, expected 0, have 1}} +} diff --git a/llvm/include/llvm/IR/IntrinsicsDirectX.td b/llvm/include/llvm/IR/IntrinsicsDirectX.td index e2b2feb927318..3810fc340962d 100644 --- a/llvm/include/llvm/IR/IntrinsicsDirectX.td +++ b/llvm/include/llvm/IR/IntrinsicsDirectX.td @@ -258,6 +258,9 @@ def int_dx_firstbituhigh : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, def int_dx_firstbitshigh : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_anyint_ty], [IntrNoMem]>; def int_dx_firstbitlow : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_anyint_ty], [IntrNoMem]>; +def int_dx_group_memory_barrier + : DefaultAttrsIntrinsic<[], [], [IntrConvergent]>; + def int_dx_group_memory_barrier_with_group_sync : DefaultAttrsIntrinsic<[], [], [IntrConvergent]>; diff --git a/llvm/include/llvm/IR/IntrinsicsSPIRV.td b/llvm/include/llvm/IR/IntrinsicsSPIRV.td index 3fc18a254f672..e1328244ef7b0 100644 --- a/llvm/include/llvm/IR/IntrinsicsSPIRV.td +++ b/llvm/include/llvm/IR/IntrinsicsSPIRV.td @@ -138,6 +138,7 @@ def int_spv_rsqrt : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty] def int_spv_wave_prefix_product : DefaultAttrsIntrinsic<[llvm_any_ty], [LLVMMatchType<0>], [IntrConvergent, IntrNoMem]>; def int_spv_sign : DefaultAttrsIntrinsic<[LLVMScalarOrSameVectorWidth<0, llvm_i32_ty>], [llvm_any_ty], [IntrNoMem]>; def int_spv_radians : DefaultAttrsIntrinsic<[LLVMMatchType<0>], [llvm_anyfloat_ty], [IntrNoMem]>; + def int_spv_group_memory_barrier : DefaultAttrsIntrinsic<[], [], [IntrConvergent]>; def int_spv_group_memory_barrier_with_group_sync : ClangBuiltin<"__builtin_spirv_group_barrier">, DefaultAttrsIntrinsic<[], [], [IntrConvergent]>; def int_spv_discard : DefaultAttrsIntrinsic<[], [], []>; diff --git a/llvm/lib/Target/DirectX/DXIL.td b/llvm/lib/Target/DirectX/DXIL.td index e64909b059d29..5ef1a7c130b4a 100644 --- a/llvm/lib/Target/DirectX/DXIL.td +++ b/llvm/lib/Target/DirectX/DXIL.td @@ -913,6 +913,8 @@ def GetDimensions : DXILOp<72, getDimensions> { def Barrier : DXILOp<80, barrier> { let Doc = "inserts a memory barrier in the shader"; let intrinsics = [ + IntrinSelect<int_dx_group_memory_barrier, + [IntrinArgI32<BarrierMode_GroupMemoryBarrier>]>, IntrinSelect<int_dx_group_memory_barrier_with_group_sync, [IntrinArgI32<BarrierMode_GroupMemoryBarrierWithGroupSync>]>, ]; diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index 7b4c047593a3a..095cc675683c5 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -336,6 +336,9 @@ class SPIRVInstructionSelector : public InstructionSelector { bool selectWaveOpInst(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I, unsigned Opcode) const; + bool selectBarrierInst(MachineInstr &I, unsigned Scope, + bool WithGroupSync) const; + bool selectWaveActiveCountBits(Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const; @@ -1893,15 +1896,15 @@ bool SPIRVInstructionSelector::selectAtomicRMW(Register ResVReg, ValueReg = TmpReg; } - BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(NewOpcode)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(Ptr) - .addUse(ScopeReg) - .addUse(MemSemReg) - .addUse(ValueReg) - .constrainAllUses(TII, TRI, RBI); - return true; + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(NewOpcode)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(Ptr) + .addUse(ScopeReg) + .addUse(MemSemReg) + .addUse(ValueReg) + .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectUnmergeValues(MachineInstr &I) const { @@ -2551,12 +2554,12 @@ bool SPIRVInstructionSelector::selectIntegerDotExpansion( for (unsigned i = 1; i < GR.getScalarOrVectorComponentCount(VecType); i++) { Register Elt = MRI->createVirtualRegister(GR.getRegClass(ResType)); - BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) - .addDef(Elt) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(TmpVec) - .addImm(i) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpCompositeExtract)) + .addDef(Elt) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(TmpVec) + .addImm(i) + .constrainAllUses(TII, TRI, RBI); Register Sum = i < GR.getScalarOrVectorComponentCount(VecType) - 1 ? MRI->createVirtualRegister(GR.getRegClass(ResType)) @@ -2757,13 +2760,13 @@ bool SPIRVInstructionSelector::selectSign(Register ResVReg, ? MRI->createVirtualRegister(&SPIRV::IDRegClass) : ResVReg; - BuildMI(BB, I, DL, TII.get(SPIRV::OpExtInst)) - .addDef(SignReg) - .addUse(GR.getSPIRVTypeID(InputType)) - .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450)) - .addImm(SignOpcode) - .addUse(InputRegister) - .constrainAllUses(TII, TRI, RBI); + BuildMI(BB, I, DL, TII.get(SPIRV::OpExtInst)) + .addDef(SignReg) + .addUse(GR.getSPIRVTypeID(InputType)) + .addImm(static_cast<uint32_t>(SPIRV::InstructionSet::GLSL_std_450)) + .addImm(SignOpcode) + .addUse(InputRegister) + .constrainAllUses(TII, TRI, RBI); if (NeedsConversion) { auto ConvertOpcode = IsFloatTy ? SPIRV::OpConvertFToS : SPIRV::OpSConvert; @@ -2798,6 +2801,27 @@ bool SPIRVInstructionSelector::selectWaveOpInst(Register ResVReg, return true; } +bool SPIRVInstructionSelector::selectBarrierInst(MachineInstr &I, + unsigned Scope, + bool WithGroupSync) const { + auto BarrierType = + WithGroupSync ? SPIRV::OpControlBarrier : SPIRV::OpMemoryBarrier; + Register MemSemReg = + buildI32Constant(SPIRV::MemorySemantics::SequentiallyConsistent, I); + Register ScopeReg = buildI32Constant(Scope, I); + MachineBasicBlock &BB = *I.getParent(); + auto MI = + BuildMI(BB, I, I.getDebugLoc(), TII.get(BarrierType)).addUse(ScopeReg); + + // OpControlBarrier needs to also set Execution Scope + if (WithGroupSync) { + MI.addUse(ScopeReg); + } + + MI.addUse(MemSemReg).constrainAllUses(TII, TRI, RBI); + return true; +} + bool SPIRVInstructionSelector::selectWaveActiveCountBits( Register ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const { @@ -3848,22 +3872,22 @@ bool SPIRVInstructionSelector::selectDerivativeInst( Register ConvertToVReg = MRI->createVirtualRegister(RegClass); Register DpdOpVReg = MRI->createVirtualRegister(RegClass); - BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert)) - .addDef(ConvertToVReg) - .addUse(GR.getSPIRVTypeID(F32ConvertTy)) - .addUse(SrcReg) - .constrainAllUses(TII, TRI, RBI); - BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DPdOpCode)) - .addDef(DpdOpVReg) - .addUse(GR.getSPIRVTypeID(F32ConvertTy)) - .addUse(ConvertToVReg) - .constrainAllUses(TII, TRI, RBI); - BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert)) - .addDef(ResVReg) - .addUse(GR.getSPIRVTypeID(ResType)) - .addUse(DpdOpVReg) - .constrainAllUses(TII, TRI, RBI); - return true; + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert)) + .addDef(ConvertToVReg) + .addUse(GR.getSPIRVTypeID(F32ConvertTy)) + .addUse(SrcReg) + .constrainAllUses(TII, TRI, RBI); + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(DPdOpCode)) + .addDef(DpdOpVReg) + .addUse(GR.getSPIRVTypeID(F32ConvertTy)) + .addUse(ConvertToVReg) + .constrainAllUses(TII, TRI, RBI); + BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpFConvert)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addUse(DpdOpVReg) + .constrainAllUses(TII, TRI, RBI); + return true; } bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, @@ -4160,18 +4184,10 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, return selectFirstBitHigh(ResVReg, ResType, I, /*IsSigned=*/true); case Intrinsic::spv_firstbitlow: // There is no CL equivlent of FindILsb return selectFirstBitLow(ResVReg, ResType, I); - case Intrinsic::spv_group_memory_barrier_with_group_sync: { - Register MemSemReg = - buildI32Constant(SPIRV::MemorySemantics::SequentiallyConsistent, I); - Register ScopeReg = buildI32Constant(SPIRV::Scope::Workgroup, I); - MachineBasicBlock &BB = *I.getParent(); - BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpControlBarrier)) - .addUse(ScopeReg) - .addUse(ScopeReg) - .addUse(MemSemReg) - .constrainAllUses(TII, TRI, RBI); - return true; - } + case Intrinsic::spv_group_memory_barrier: + return selectBarrierInst(I, SPIRV::Scope::Workgroup, false); + case Intrinsic::spv_group_memory_barrier_with_group_sync: + return selectBarrierInst(I, SPIRV::Scope::Workgroup, true); case Intrinsic::spv_generic_cast_to_ptr_explicit: { Register PtrReg = I.getOperand(I.getNumExplicitDefs() + 1).getReg(); SPIRV::StorageClass::StorageClass ResSC = @@ -4333,8 +4349,8 @@ bool SPIRVInstructionSelector::selectIntrinsic(Register ResVReg, bool SPIRVInstructionSelector::selectHandleFromBinding(Register &ResVReg, SPIRVTypeInst ResType, MachineInstr &I) const { - // The images need to be loaded in the same basic block as their use. We defer - // loading the image to the intrinsic that uses it. + // The images need to be loaded in the same basic block as their use. We + // defer loading the image to the intrinsic that uses it. if (ResType->getOpcode() == SPIRV::OpTypeImage) return true; @@ -4381,9 +4397,9 @@ bool SPIRVInstructionSelector::selectUpdateCounter(Register &ResVReg, Register CounterHandleReg = Intr.getOperand(2).getReg(); Register IncrReg = Intr.getOperand(3).getReg(); - // The counter handle is a pointer to the counter variable (which is a struct - // containing an i32). We need to get a pointer to that i32 member to do the - // atomic operation. + // The counter handle is a pointer to the counter variable (which is a + // struct containing an i32). We need to get a pointer to that i32 member to + // do the atomic operation. #ifndef NDEBUG SPIRVTypeInst CounterVarType = GR.getSPIRVTypeForVReg(CounterHandleReg); SPIRVTypeInst CounterVarPointeeType = GR.getPointeeType(CounterVarType); @@ -4442,8 +4458,8 @@ bool SPIRVInstructionSelector::selectUpdateCounter(Register &ResVReg, } // In HLSL, IncrementCounter returns the value *before* the increment, while - // DecrementCounter returns the value *after* the decrement. Both are lowered - // to the same atomic intrinsic which returns the value *before* the + // DecrementCounter returns the value *after* the decrement. Both are + // lowered to the same atomic intrinsic which returns the value *before* the // operation. So for decrements (negative IncrVal), we must subtract the // increment value from the result to get the post-decrement value. BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(SPIRV::OpIAddS)) @@ -4462,8 +4478,8 @@ bool SPIRVInstructionSelector::selectReadImageIntrinsic(Register &ResVReg, // this will generate invalid code. A proper solution is to move // the OpLoad from selectHandleFromBinding here. However, to do // that we will need to change the return type of the intrinsic. - // We will do that when we can, but for now trying to move forward with other - // issues. + // We will do that when we can, but for now trying to move forward with + // other issues. Register ImageReg = I.getOperand(2).getReg(); auto *ImageDef = cast<GIntrinsic>(getVRegDef(*MRI, ImageReg)); Register NewImageReg = MRI->createVirtualRegister(MRI->getRegClass(ImageReg)); @@ -4682,8 +4698,8 @@ bool SPIRVInstructionSelector::selectGatherIntrinsic(Register &ResVReg, auto Dim = static_cast<SPIRV::Dim::Dim>(ImageType->getOperand(2).getImm()); if (Dim != SPIRV::Dim::DIM_2D && Dim != SPIRV::Dim::DIM_Cube && Dim != SPIRV::Dim::DIM_Rect) { - I.emitGenericError( - "Gather operations are only supported for 2D, Cube, and Rect images."); + I.emitGenericError("Gather operations are only supported for 2D, Cube, " + "and Rect images."); return false; } @@ -4806,10 +4822,10 @@ bool SPIRVInstructionSelector::selectResourceGetPointer(Register &ResVReg, Register ResourcePtr = I.getOperand(2).getReg(); SPIRVTypeInst RegType = GR.getSPIRVTypeForVReg(ResourcePtr, I.getMF()); if (RegType->getOpcode() == SPIRV::OpTypeImage) { - // For texel buffers, the index into the image is part of the OpImageRead or - // OpImageWrite instructions. So we will do nothing in this case. This - // intrinsic will be combined with the load or store when selecting the load - // or store. + // For texel buffers, the index into the image is part of the OpImageRead + // or OpImageWrite instructions. So we will do nothing in this case. This + // intrinsic will be combined with the load or store when selecting the + // load or store. return true; } @@ -4927,8 +4943,8 @@ bool SPIRVInstructionSelector::selectImageWriteIntrinsic( // this will generate invalid code. A proper solution is to move // the OpLoad from selectHandleFromBinding here. However, to do // that we will need to change the return type of the intrinsic. - // We will do that when we can, but for now trying to move forward with other - // issues. + // We will do that when we can, but for now trying to move forward with + // other issues. Register ImageReg = I.getOperand(1).getReg(); auto *ImageDef = cast<GIntrinsic>(getVRegDef(*MRI, ImageReg)); Register NewImageReg = MRI->createVirtualRegister(MRI->getRegClass(ImageReg)); @@ -5246,8 +5262,8 @@ bool SPIRVInstructionSelector::selectFirstBitHigh(Register ResVReg, return selectFirstBitSet64(ResVReg, ResType, I, OpReg, BitSetOpcode, /*SwapPrimarySide=*/false); default: - report_fatal_error( - "spv_firstbituhigh and spv_firstbitshigh only support 16,32,64 bits."); + report_fatal_error("spv_firstbituhigh and spv_firstbitshigh only support " + "16,32,64 bits."); } } @@ -5258,8 +5274,8 @@ bool SPIRVInstructionSelector::selectFirstBitLow(Register ResVReg, Register OpReg = I.getOperand(2).getReg(); SPIRVTypeInst OpType = GR.getSPIRVTypeForVReg(OpReg); // OpUConvert treats the operand bits as an unsigned i16 and zero extends it - // to an unsigned i32. As this leaves all the least sig... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/185383 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
