Author: Ramkumar Ramachandra Date: 2026-03-10T08:40:49Z New Revision: c1f3cb73a0da4294b7c745488a224f6b51fd408c
URL: https://github.com/llvm/llvm-project/commit/c1f3cb73a0da4294b7c745488a224f6b51fd408c DIFF: https://github.com/llvm/llvm-project/commit/c1f3cb73a0da4294b7c745488a224f6b51fd408c.diff LOG: [RISCV] Make zvknha a subset of zvknhb (#178680) zvknha is a strict subset of zvknhb. Treat it as such. Ref: https://github.com/riscv/riscv-isa-manual/blob/main/src/vector-crypto.adoc#zvknh Added: Modified: clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c clang/test/Driver/riscv-cpus.c clang/test/Preprocessor/riscv-target-features.c llvm/lib/Target/RISCV/RISCVFeatures.td llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/attribute-arch.s llvm/test/MC/RISCV/rvv/zvknh.s llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp Removed: ################################################################################ diff --git a/clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c b/clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c index e50768a62e6eb..c7a9d80554f9c 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c @@ -64,6 +64,7 @@ // CHECK-NEXT: zvknc 1.0 'Zvknc' (shorthand for 'Zvknc' and 'Zvbc') // CHECK-NEXT: zvkned 1.0 'Zvkned' (Vector AES Encryption & Decryption (Single Round)) // CHECK-NEXT: zvkng 1.0 'Zvkng' (shorthand for 'Zvkn' and 'Zvkg') +// CHECK-NEXT: zvknha 1.0 'Zvknha' (Vector SHA-2 (SHA-256 only)) // CHECK-NEXT: zvknhb 1.0 'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512)) // CHECK-NEXT: zvks 1.0 'Zvks' (shorthand for 'Zvksed', 'Zvksh', 'Zvkb', and 'Zvkt') // CHECK-NEXT: zvksc 1.0 'Zvksc' (shorthand for 'Zvks' and 'Zvbc') @@ -78,4 +79,4 @@ // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions // CHECK-EMPTY: -// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zama16b1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkr1p0_zkt1p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfbfwma1p0_zvfh1p0_zvfhmin1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0 +// CHECK-NEXT: ISA String: rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_b1p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zaamo1p0_zalrsc1p0_zama16b1p0_zawrs1p0_zfa1p0_zfbfmin1p0_zfh1p0_zfhmin1p0_zca1p0_zcb1p0_zcd1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkr1p0_zkt1p0_zvbb1p0_zvbc1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfbfmin1p0_zvfbfwma1p0_zvfh1p0_zvfhmin1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksg1p0_zvksh1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_supm1p0 diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 1326681a8d6cb..64b8cc27974fd 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -266,6 +266,7 @@ // MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvknc" // MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvkned" // MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvkng" +// MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvknha" // MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvknhb" // MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvkt" // MCPU-TT-ASCALON-X-SAME: "-target-feature" "+zvl128b" diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index db1b7b1a36d56..501a66080c2b7 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -1480,6 +1480,17 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-ZVKNG %s // CHECK-COMBINE-INTO-ZVKNG: __riscv_zvkn 1000000{{$}} // CHECK-COMBINE-INTO-ZVKNG: __riscv_zvkng 1000000{{$}} +// CHECK-COMBINE-INTO-ZVKNG: __riscv_zvknha 1000000{{$}} +// CHECK-COMBINE-INTO-ZVKNG: __riscv_zvknhb 1000000{{$}} + +// RUN: %clang --target=riscv32 \ +// RUN: -march=rv32iv_zvknhb1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-ZVKNHB %s +// RUN: %clang --target=riscv64 \ +// RUN: -march=rv64iv_zvknhb1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-COMBINE-INTO-ZVKNHB %s +// CHECK-COMBINE-INTO-ZVKNHB: __riscv_zvknha 1000000{{$}} +// CHECK-COMBINE-INTO-ZVKNHB: __riscv_zvknhb 1000000{{$}} // RUN: %clang --target=riscv32 \ // RUN: -march=rv32i_zve32x_zvknha1p0 -E -dM %s \ diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index e5013b166b047..7d3af9349ae24 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -818,16 +818,12 @@ def HasStdExtZvknha : Predicate<"Subtarget->hasStdExtZvknha()">, def FeatureStdExtZvknhb : RISCVExtension<1, 0, "Vector SHA-2 (SHA-256 and SHA-512)", - [FeatureStdExtZve64x]>, + [FeatureStdExtZve64x, FeatureStdExtZvknha]>, RISCVExtensionBitmask<0, 56>; def HasStdExtZvknhb : Predicate<"Subtarget->hasStdExtZvknhb()">, AssemblerPredicate<(all_of FeatureStdExtZvknhb), "'Zvknhb' (Vector SHA-2 (SHA-256 and SHA-512))">; -def HasStdExtZvknhaOrZvknhb : Predicate<"Subtarget->hasStdExtZvknha() || Subtarget->hasStdExtZvknhb()">, - AssemblerPredicate<(any_of FeatureStdExtZvknha, FeatureStdExtZvknhb), - "'Zvknha' or 'Zvknhb' (Vector SHA-2)">; - def FeatureStdExtZvksed : RISCVExtension<1, 0, "SM4 Block Cipher Instructions", [FeatureStdExtZve32x]>, diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td index 58ce46d3eba4a..fd9e6f282e60b 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td @@ -158,7 +158,7 @@ let Predicates = [HasStdExtZvkgs], VS1VS2Constraint = VS2Constraint in { SchedBinaryMC<"WriteVGMULV", "ReadVGMULV", "ReadVGMULV">; } // Predicates = [HasStdExtZvkgs] -let Predicates = [HasStdExtZvknhaOrZvknhb], VS1VS2Constraint = Sha2Constraint in { +let Predicates = [HasStdExtZvknha], VS1VS2Constraint = Sha2Constraint in { def VSHA2CH_VV : ZvkALUVVNoVmTernary<0b101110, OPMVV, "vsha2ch.vv">, SchedTernaryMC<"WriteVSHA2CHV", "ReadVSHA2CHV", "ReadVSHA2CHV", "ReadVSHA2CHV">; @@ -168,7 +168,7 @@ let Predicates = [HasStdExtZvknhaOrZvknhb], VS1VS2Constraint = Sha2Constraint in def VSHA2MS_VV : ZvkALUVVNoVmTernary<0b101101, OPMVV, "vsha2ms.vv">, SchedTernaryMC<"WriteVSHA2MSV", "ReadVSHA2MSV", "ReadVSHA2MSV", "ReadVSHA2MSV">; -} // Predicates = [HasStdExtZvknhaOrZvknhb] +} // Predicates = [HasStdExtZvknha] let Predicates = [HasStdExtZvkned] in { defm VAESDF : VAES_MV_V_S<0b101000, 0b101001, 0b00001, OPMVV, "vaesdf">; @@ -555,13 +555,13 @@ let Predicates = [HasStdExtZvkned] in { defm PseudoVAESZ : VPseudoVAESZ; } // Predicates = [HasStdExtZvkned] -let Predicates = [HasStdExtZvknhaOrZvknhb] in { +let Predicates = [HasStdExtZvknha] in { defm PseudoVSHA2CH : VPseudoVSHA2CH; defm PseudoVSHA2CL : VPseudoVSHA2CL; defm PseudoVSHA2MS : VPseudoVSHA2MS<sew=32>; let Predicates = [HasStdExtZvknhb] in defm PseudoVSHA2MS : VPseudoVSHA2MS<sew=64>; -} // Predicates = [HasStdExtZvknhaOrZvknhb] +} // Predicates = [HasStdExtZvknha] let Predicates = [HasStdExtZvksed] in { defm PseudoVSM4K : VPseudoVSM4K; @@ -1130,9 +1130,9 @@ defm : VPatBinaryV_VI_NoMaskTU<"int_riscv_vaeskf1", "PseudoVAESKF1", I32IntegerV defm : VPatBinaryV_VI_NoMask<"int_riscv_vaeskf2", "PseudoVAESKF2", I32IntegerVectors, [HasStdExtZvkned]>; defm : VPatUnaryV_S_NoMaskVectorCrypto<"int_riscv_vaesz", "PseudoVAESZ", I32IntegerVectors, [HasStdExtZvkned] >; -defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ch", "PseudoVSHA2CH", I32IntegerVectors, [HasStdExtZvknhaOrZvknhb]>; -defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CL", I32IntegerVectors, [HasStdExtZvknhaOrZvknhb]>; -defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS", I32IntegerVectors, [HasStdExtZvknhaOrZvknhb], isSEWAware=true>; +defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ch", "PseudoVSHA2CH", I32IntegerVectors, [HasStdExtZvknha]>; +defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CL", I32IntegerVectors, [HasStdExtZvknha]>; +defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ms", "PseudoVSHA2MS", I32IntegerVectors, [HasStdExtZvknha], isSEWAware=true>; defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2ch", "PseudoVSHA2CH", I64IntegerVectors, [HasStdExtZvknhb]>; defm : VPatBinaryV_VV_NoMask<"int_riscv_vsha2cl", "PseudoVSHA2CL", I64IntegerVectors, [HasStdExtZvknhb]>; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index c366521066218..7a68440127dd9 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -418,12 +418,12 @@ ; RV32ZVBC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0" ; RV32ZVKB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvl32b1p0" ; RV32ZVKG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0" -; RV32ZVKN: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" -; RV32ZVKNC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" +; RV32ZVKN: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" +; RV32ZVKNC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" ; RV32ZVKNED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0" -; RV32ZVKNG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" +; RV32ZVKNG: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" ; RV32ZVKNHA: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0" -; RV32ZVKNHB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0" +; RV32ZVKNHB: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0" ; RV32ZVKS: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" ; RV32ZVKSC: .attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" ; RV32ZVKSED: .attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvksed1p0_zvl32b1p0" @@ -571,12 +571,12 @@ ; RV64ZVBC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvl32b1p0_zvl64b1p0" ; RV64ZVKB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvl32b1p0" ; RV64ZVKG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0" -; RV64ZVKN: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" -; RV64ZVKNC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" +; RV64ZVKN: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" +; RV64ZVKNC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" ; RV64ZVKNED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0" -; RV64ZVKNG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" +; RV64ZVKNG: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" ; RV64ZVKNHA: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0" -; RV64ZVKNHB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0" +; RV64ZVKNHB: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0" ; RV64ZVKS: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvkb1p0_zvks1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0" ; RV64ZVKSC: .attribute 5, "rv64i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvks1p0_zvksc1p0_zvksed1p0_zvksh1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" ; RV64ZVKSED: .attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvksed1p0_zvl32b1p0" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 4be441412693d..90ff008b9cc1d 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -142,19 +142,19 @@ # CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkg1p0_zvl32b1p0" .attribute arch, "rv32i_zve64x_zvkn1p0" -# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" +# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" .attribute arch, "rv32i_zve64x_zvknc1p0" -# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" +# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zvbc1p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkn1p0_zvknc1p0_zvkned1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" .attribute arch, "rv32i_zve64x_zvkng1p0" -# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" +# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvkb1p0_zvkg1p0_zvkn1p0_zvkned1p0_zvkng1p0_zvknha1p0_zvknhb1p0_zvkt1p0_zvl32b1p0_zvl64b1p0" .attribute arch, "rv32i_zve32x_zvknha1p0" # CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvknha1p0_zvl32b1p0" .attribute arch, "rv32i_zve64x_zvknhb1p0" -# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0" +# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zve64x1p0_zvknha1p0_zvknhb1p0_zvl32b1p0_zvl64b1p0" .attribute arch, "rv32i_zve32x_zvkned1p0" # CHECK: attribute 5, "rv32i2p1_zicsr2p0_zve32x1p0_zvkned1p0_zvl32b1p0" diff --git a/llvm/test/MC/RISCV/rvv/zvknh.s b/llvm/test/MC/RISCV/rvv/zvknh.s index b16b9081f7e63..17b521671b4e3 100644 --- a/llvm/test/MC/RISCV/rvv/zvknh.s +++ b/llvm/test/MC/RISCV/rvv/zvknh.s @@ -19,16 +19,16 @@ vsha2ms.vv v10, v9, v8 # CHECK-INST: vsha2ms.vv v10, v9, v8 # CHECK-ENCODING: [0x77,0x25,0x94,0xb6] # CHECK-UNKNOWN: b6942577 <unknown> -# CHECK-ERROR: instruction requires the following: 'Zvknha' or 'Zvknhb' (Vector SHA-2){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2 (SHA-256 only)){{$}} vsha2ch.vv v10, v9, v8 # CHECK-INST: vsha2ch.vv v10, v9, v8 # CHECK-ENCODING: [0x77,0x25,0x94,0xba] # CHECK-UNKNOWN: ba942577 <unknown> -# CHECK-ERROR: instruction requires the following: 'Zvknha' or 'Zvknhb' (Vector SHA-2){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2 (SHA-256 only)){{$}} vsha2cl.vv v10, v9, v8 # CHECK-INST: vsha2cl.vv v10, v9, v8 # CHECK-ENCODING: [0x77,0x25,0x94,0xbe] # CHECK-UNKNOWN: be942577 <unknown> -# CHECK-ERROR: instruction requires the following: 'Zvknha' or 'Zvknhb' (Vector SHA-2){{$}} +# CHECK-ERROR: instruction requires the following: 'Zvknha' (Vector SHA-2 (SHA-256 only)){{$}} diff --git a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp index 6eeb07f1cf279..887df7ac7b393 100644 --- a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp +++ b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp @@ -101,7 +101,7 @@ template <class BaseT> class RISCVSnippetGenerator : public BaseT { return 128U; if (isOpcodeAvailableIn(Opcode, {Feature_HasStdExtZvkshBit})) return 256U; - if (isOpcodeAvailableIn(Opcode, {Feature_HasStdExtZvknhaOrZvknhbBit})) + if (isOpcodeAvailableIn(Opcode, {Feature_HasStdExtZvknhaBit})) // In Zvknh[ab], when SEW=64 is used (i.e. Zvknhb), EGW is 256. // Otherwise it's 128. return SEW == 64 ? 256U : 128U; @@ -400,14 +400,14 @@ void RISCVSnippetGenerator<BaseT>::annotateWithVType( using namespace RISCV_MC; if (isOpcodeAvailableIn(BaseOpcode, {Feature_HasStdExtZvkgBit, Feature_HasStdExtZvknedBit, - Feature_HasStdExtZvknhaOrZvknhbBit, + Feature_HasStdExtZvknhaBit, Feature_HasStdExtZvksedBit, Feature_HasStdExtZvkshBit})) { if (*SEW != 32) // Zvknhb supports SEW=64 as well. if (*SEW != 64 || !STI.hasFeature(RISCV::FeatureStdExtZvknhb) || !isOpcodeAvailableIn(BaseOpcode, - {Feature_HasStdExtZvknhaOrZvknhbBit})) { + {Feature_HasStdExtZvknhaBit})) { SEW = SEWCandidates.erase(SEW); continue; } _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
