https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/185617
None >From 140e59a204aaa1cd4a19b4427a415915653bd877 Mon Sep 17 00:00:00 2001 From: Pengcheng Wang <[email protected]> Date: Tue, 10 Mar 2026 19:09:08 +0800 Subject: [PATCH] [RISCV] Add release notes for Zvabd --- clang/docs/ReleaseNotes.rst | 1 + llvm/docs/ReleaseNotes.md | 1 + 2 files changed, 2 insertions(+) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 5d07bfc210e05..a3ae235990b13 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -409,6 +409,7 @@ RISC-V Support ^^^^^^^^^^^^^^ - Tenstorrent Ascalon D8 was renamed to Ascalon X. Use `tt-ascalon-x` with `-mcpu` or `-mtune`. +- Adds intrinsics for the 'Zvabd` (RISC-V Integer Vector Absolute Difference) extension. CUDA/HIP Language Changes ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 91b150c9fe982..098162b0a4c9a 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -153,6 +153,7 @@ Changes to the RISC-V Backend extensions. * Adds experimental assembler support for the 'Zvabd` (RISC-V Integer Vector Absolute Difference) extension. +* Adds CodeGen support for the 'Zvabd` extension. * `-mcpu=spacemit-a100` was added. * The opt-in `-riscv-enable-p-ext-simd-codegen` flag has been removed. P extension SIMD code generation is now enabled automatically if the P extension is supported. * `-mcpu=xt-c910v2` and `-mcpu=xt-c920v2` were added. _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
