================ @@ -0,0 +1,103 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This contains code to emit RISC-V Builtin calls as CIR or a function call +// to be later resolved. +// +//===----------------------------------------------------------------------===// + +#include "CIRGenFunction.h" +#include "clang/Basic/TargetBuiltins.h" + +using namespace clang; +using namespace clang::CIRGen; + +std::optional<mlir::Value> +CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID, const CallExpr *e) { + switch (builtinID) { + default: + return std::nullopt; + + // Zihintpause + case RISCV::BI__builtin_riscv_pause: ---------------- andykaylor wrote:
The order here doesn't match the order in clang/lib/CodeGen/TargetBuiltins/RISCV.cpp, which makes it difficult to assess if there are entries missing. https://github.com/llvm/llvm-project/pull/186050 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
