trungnt2910 wrote: Seems like it's not a good idea to modify existing intrinsics 😅
I updated the PR to no longer rely on the 4th parameter and try to restore R1. Instead, for functions that has SEH, we force enabling the base register (R6). R6 is always preserved by the runtime on ARM (and ARM64 as well) when transferring control to the SEH handlers. This also matches what MSVC is doing - the only difference is that they seem to use R7 instead. https://github.com/llvm/llvm-project/pull/184953 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
