================
@@ -2781,8 +2804,17 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned
builtinID, const CallExpr *expr,
case NEON::BI__builtin_neon_vqshlud_n_s64:
case NEON::BI__builtin_neon_vqshld_n_u64:
case NEON::BI__builtin_neon_vqshld_n_s64:
- case NEON::BI__builtin_neon_vrshrd_n_u64:
case NEON::BI__builtin_neon_vrshrd_n_s64:
+ case NEON::BI__builtin_neon_vrshrd_n_u64: {
+ // srshl/urshl are left-shift intrinsics; passing -n performs a rounding
+ // right-shift by n.
+ bool isSigned = builtinID == NEON::BI__builtin_neon_vrshrd_n_s64;
+ mlir::Value negShift = builder.createNeg(
+ builder.createIntCast(ops[1], builder.getSIntNTy(64)));
+ return builder.emitIntrinsicCallOp(
+ loc, isSigned ? "aarch64.neon.srshl" : "aarch64.neon.urshl",
+ convertType(expr->getType()), mlir::ValueRange{ops[0], negShift});
----------------
banach-space wrote:
Could you re-write this via
https://github.com/llvm/llvm-project/blob/3b3f3730351cd59a849663700b07d7643a7f74a1/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp?plain=1#L1342-L1352
? We want to match:
https://github.com/llvm/llvm-project/blob/3b3f3730351cd59a849663700b07d7643a7f74a1/clang/lib/CodeGen/TargetBuiltins/ARM.cpp?plain=1#L6494-L6502
and:
https://github.com/llvm/clangir/blob/main/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp#L4084-L4100
https://github.com/llvm/llvm-project/pull/185992
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