================
@@ -0,0 +1,255 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve2p3 < %s | FileCheck %s
--check-prefix=SVE2P3
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve,+sme2p3 < %s | FileCheck %s
--check-prefix=SME2P3
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme2p3 -force-streaming < %s |
FileCheck %s --check-prefix=STR
+;
+; SVCVTB (SCVTFB / UCVTFB)
+;
+
+define <vscale x 8 x half> @scvtfb_f16_i8(<vscale x 16 x i8> %zn) {
+; SVE2P3-LABEL: scvtfb_f16_i8:
+; SVE2P3: // %bb.0:
+; SVE2P3-NEXT: scvtf z0.h, z0.b
+; SVE2P3-NEXT: ret
+;
+; SME2P3-LABEL: scvtfb_f16_i8:
+; SME2P3: // %bb.0:
+; SME2P3-NEXT: scvtf z0.h, z0.b
+; SME2P3-NEXT: ret
+;
+; STR-LABEL: scvtfb_f16_i8:
+; STR: // %bb.0:
+; STR-NEXT: scvtf z0.h, z0.b
+; STR-NEXT: ret
+ %res = call <vscale x 8 x half> @llvm.aarch64.sve.scvtfb.f16i8(<vscale x 16
x i8> %zn)
+ ret <vscale x 8 x half> %res
+}
+
+define <vscale x 4 x float> @scvtfb_f32_i16(<vscale x 8 x i16> %zn) {
+; SVE2P3-LABEL: scvtfb_f32_i16:
+; SVE2P3: // %bb.0:
+; SVE2P3-NEXT: scvtf z0.s, z0.h
+; SVE2P3-NEXT: ret
+;
+; SME2P3-LABEL: scvtfb_f32_i16:
+; SME2P3: // %bb.0:
+; SME2P3-NEXT: scvtf z0.s, z0.h
+; SME2P3-NEXT: ret
+;
+; STR-LABEL: scvtfb_f32_i16:
+; STR: // %bb.0:
+; STR-NEXT: scvtf z0.s, z0.h
+; STR-NEXT: ret
+ %res = call <vscale x 4 x float> @llvm.aarch64.sve.scvtfb.f32i16(<vscale x 8
x i16> %zn)
+ ret <vscale x 4 x float> %res
+}
+
+define <vscale x 2 x double> @scvtfb_f64_i32(<vscale x 4 x i32> %zn) {
+; SVE2P3-LABEL: scvtfb_f64_i32:
+; SVE2P3: // %bb.0:
+; SVE2P3-NEXT: scvtf z0.d, z0.s
+; SVE2P3-NEXT: ret
+;
+; SME2P3-LABEL: scvtfb_f64_i32:
+; SME2P3: // %bb.0:
+; SME2P3-NEXT: scvtf z0.d, z0.s
+; SME2P3-NEXT: ret
+;
+; STR-LABEL: scvtfb_f64_i32:
+; STR: // %bb.0:
+; STR-NEXT: scvtf z0.d, z0.s
+; STR-NEXT: ret
+ %res = call <vscale x 2 x double> @llvm.aarch64.sve.scvtfb.f64i32(<vscale x
4 x i32> %zn)
+ ret <vscale x 2 x double> %res
+}
+
+define <vscale x 8 x half> @ucvtfb_f16_i8(<vscale x 16 x i8> %zn) {
+; SVE2P3-LABEL: ucvtfb_f16_i8:
+; SVE2P3: // %bb.0:
+; SVE2P3-NEXT: ucvtf z0.h, z0.b
+; SVE2P3-NEXT: ret
+;
+; SME2P3-LABEL: ucvtfb_f16_i8:
+; SME2P3: // %bb.0:
+; SME2P3-NEXT: ucvtf z0.h, z0.b
+; SME2P3-NEXT: ret
+;
+; STR-LABEL: ucvtfb_f16_i8:
+; STR: // %bb.0:
+; STR-NEXT: ucvtf z0.h, z0.b
+; STR-NEXT: ret
+ %res = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtfb.f16i8(<vscale x 16
x i8> %zn)
+ ret <vscale x 8 x half> %res
+}
+
+define <vscale x 4 x float> @ucvtfb_f32_i16(<vscale x 8 x i16> %zn) {
+; SVE2P3-LABEL: ucvtfb_f32_i16:
+; SVE2P3: // %bb.0:
+; SVE2P3-NEXT: ucvtf z0.s, z0.h
+; SVE2P3-NEXT: ret
+;
+; SME2P3-LABEL: ucvtfb_f32_i16:
+; SME2P3: // %bb.0:
+; SME2P3-NEXT: ucvtf z0.s, z0.h
+; SME2P3-NEXT: ret
+;
+; STR-LABEL: ucvtfb_f32_i16:
+; STR: // %bb.0:
+; STR-NEXT: ucvtf z0.s, z0.h
+; STR-NEXT: ret
+ %res = call <vscale x 4 x float> @llvm.aarch64.sve.ucvtfb.f32i16(<vscale x 8
x i16> %zn)
+ ret <vscale x 4 x float> %res
+}
+
+define <vscale x 2 x double> @ucvtfb_f64_i32(<vscale x 4 x i32> %zn) {
+; SVE2P3-LABEL: ucvtfb_f64_i32:
+; SVE2P3: // %bb.0:
+; SVE2P3-NEXT: ucvtf z0.d, z0.s
+; SVE2P3-NEXT: ret
+;
+; SME2P3-LABEL: ucvtfb_f64_i32:
+; SME2P3: // %bb.0:
+; SME2P3-NEXT: ucvtf z0.d, z0.s
+; SME2P3-NEXT: ret
+;
+; STR-LABEL: ucvtfb_f64_i32:
+; STR: // %bb.0:
+; STR-NEXT: ucvtf z0.d, z0.s
+; STR-NEXT: ret
+ %res = call <vscale x 2 x double> @llvm.aarch64.sve.ucvtfb.f64i32(<vscale x
4 x i32> %zn)
+ ret <vscale x 2 x double> %res
+}
+
+;
+; SVCVTT (SCVTFLT / UCVTFLT)
+;
+
+define <vscale x 8 x half> @scvtflt_f16_i8(<vscale x 16 x i8> %zn) {
+; SVE2P3-LABEL: scvtflt_f16_i8:
+; SVE2P3: // %bb.0:
+; SVE2P3-NEXT: scvtflt z0.h, z0.b
+; SVE2P3-NEXT: ret
+;
+; SME2P3-LABEL: scvtflt_f16_i8:
+; SME2P3: // %bb.0:
+; SME2P3-NEXT: scvtflt z0.h, z0.b
+; SME2P3-NEXT: ret
+;
+; STR-LABEL: scvtflt_f16_i8:
+; STR: // %bb.0:
+; STR-NEXT: scvtflt z0.h, z0.b
+; STR-NEXT: ret
+ %res = call <vscale x 8 x half> @llvm.aarch64.sve.scvtflt.f16i8(<vscale x 16
x i8> %zn)
+ ret <vscale x 8 x half> %res
+}
+
+define <vscale x 4 x float> @scvtflt_f32_i16(<vscale x 8 x i16> %zn) {
+; SVE2P3-LABEL: scvtflt_f32_i16:
+; SVE2P3: // %bb.0:
+; SVE2P3-NEXT: scvtflt z0.s, z0.h
+; SVE2P3-NEXT: ret
+;
+; SME2P3-LABEL: scvtflt_f32_i16:
+; SME2P3: // %bb.0:
+; SME2P3-NEXT: scvtflt z0.s, z0.h
+; SME2P3-NEXT: ret
+;
+; STR-LABEL: scvtflt_f32_i16:
+; STR: // %bb.0:
+; STR-NEXT: scvtflt z0.s, z0.h
+; STR-NEXT: ret
+ %res = call <vscale x 4 x float> @llvm.aarch64.sve.scvtflt.f32i16(<vscale x
8 x i16> %zn)
+ ret <vscale x 4 x float> %res
+}
+
+define <vscale x 2 x double> @scvtflt_f64_i32(<vscale x 4 x i32> %zn) {
+; SVE2P3-LABEL: scvtflt_f64_i32:
+; SVE2P3: // %bb.0:
+; SVE2P3-NEXT: scvtflt z0.d, z0.s
+; SVE2P3-NEXT: ret
+;
+; SME2P3-LABEL: scvtflt_f64_i32:
+; SME2P3: // %bb.0:
+; SME2P3-NEXT: scvtflt z0.d, z0.s
+; SME2P3-NEXT: ret
+;
+; STR-LABEL: scvtflt_f64_i32:
+; STR: // %bb.0:
+; STR-NEXT: scvtflt z0.d, z0.s
+; STR-NEXT: ret
+ %res = call <vscale x 2 x double> @llvm.aarch64.sve.scvtflt.f64i32(<vscale x
4 x i32> %zn)
+ ret <vscale x 2 x double> %res
+}
+
+define <vscale x 8 x half> @ucvtflt_f16_i8(<vscale x 16 x i8> %zn) {
+; SVE2P3-LABEL: ucvtflt_f16_i8:
+; SVE2P3: // %bb.0:
+; SVE2P3-NEXT: ucvtflt z0.h, z0.b
+; SVE2P3-NEXT: ret
+;
+; SME2P3-LABEL: ucvtflt_f16_i8:
+; SME2P3: // %bb.0:
+; SME2P3-NEXT: ucvtflt z0.h, z0.b
+; SME2P3-NEXT: ret
+;
+; STR-LABEL: ucvtflt_f16_i8:
+; STR: // %bb.0:
+; STR-NEXT: ucvtflt z0.h, z0.b
+; STR-NEXT: ret
+ %res = call <vscale x 8 x half> @llvm.aarch64.sve.ucvtflt.f16i8(<vscale x 16
x i8> %zn)
+ ret <vscale x 8 x half> %res
+}
+
+define <vscale x 4 x float> @ucvtflt_f32_i16(<vscale x 8 x i16> %zn) {
+; SVE2P3-LABEL: ucvtflt_f32_i16:
+; SVE2P3: // %bb.0:
+; SVE2P3-NEXT: ucvtflt z0.s, z0.h
+; SVE2P3-NEXT: ret
+;
+; SME2P3-LABEL: ucvtflt_f32_i16:
+; SME2P3: // %bb.0:
+; SME2P3-NEXT: ucvtflt z0.s, z0.h
+; SME2P3-NEXT: ret
+;
+; STR-LABEL: ucvtflt_f32_i16:
+; STR: // %bb.0:
+; STR-NEXT: ucvtflt z0.s, z0.h
+; STR-NEXT: ret
+ %res = call <vscale x 4 x float> @llvm.aarch64.sve.ucvtflt.f32i16(<vscale x
8 x i16> %zn)
+ ret <vscale x 4 x float> %res
+}
+
+define <vscale x 2 x double> @ucvtflt_f64_i32(<vscale x 4 x i32> %zn) {
+; SVE2P3-LABEL: ucvtflt_f64_i32:
+; SVE2P3: // %bb.0:
+; SVE2P3-NEXT: ucvtflt z0.d, z0.s
+; SVE2P3-NEXT: ret
+;
+; SME2P3-LABEL: ucvtflt_f64_i32:
+; SME2P3: // %bb.0:
+; SME2P3-NEXT: ucvtflt z0.d, z0.s
+; SME2P3-NEXT: ret
+;
+; STR-LABEL: ucvtflt_f64_i32:
+; STR: // %bb.0:
+; STR-NEXT: ucvtflt z0.d, z0.s
+; STR-NEXT: ret
+ %res = call <vscale x 2 x double> @llvm.aarch64.sve.ucvtflt.f64i32(<vscale x
4 x i32> %zn)
+ ret <vscale x 2 x double> %res
+}
+
+declare <vscale x 8 x half> @llvm.aarch64.sve.scvtfb.f16i8(<vscale x 16 x i8>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.scvtfb.f32i16(<vscale x 8 x
i16>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.scvtfb.f64i32(<vscale x 4 x
i32>)
+
+declare <vscale x 8 x half> @llvm.aarch64.sve.ucvtfb.f16i8(<vscale x 16 x i8>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.ucvtfb.f32i16(<vscale x 8 x
i16>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.ucvtfb.f64i32(<vscale x 4 x
i32>)
+
+declare <vscale x 8 x half> @llvm.aarch64.sve.scvtflt.f16i8(<vscale x 16 x i8>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.scvtflt.f32i16(<vscale x 8 x
i16>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.scvtflt.f64i32(<vscale x 4 x
i32>)
+
+declare <vscale x 8 x half> @llvm.aarch64.sve.ucvtflt.f16i8(<vscale x 16 x i8>)
+declare <vscale x 4 x float> @llvm.aarch64.sve.ucvtflt.f32i16(<vscale x 8 x
i16>)
+declare <vscale x 2 x double> @llvm.aarch64.sve.ucvtflt.f64i32(<vscale x 4 x
i32>)
----------------
kmclaughlin-arm wrote:
These lines can be removed as declaring the intrinsics is no longer required in
tests like this.
https://github.com/llvm/llvm-project/pull/186807
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