================
@@ -33,33 +33,27 @@ void check__sys(__int64 v) {
__int64 ret;
__sys(ARM64_DC_CGDSW_EL1, v);
-// CHECK-ASM: msr S1_0_C7_C10_6, x8
+// CHECK-ASM: sys #0, c7, c10, #6, x8
// CHECK-IR: %[[VAR:.*]] = load i64,
-// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD2:.*]], i64
%[[VAR]])
+// CHECK-IR-NEXT: call void @llvm.aarch64.sys(i32 0, i32 7, i32 10, i32 6, i64
%[[VAR]])
__sys(ARM64_IC_IALLU_EL1, v);
-// CHECK-ASM: msr S1_0_C7_C5_0, x8
+// CHECK-ASM: sys #0, c7, c5, #0, x8
// CHECK-IR: %[[VAR:.*]] = load i64,
-// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD3:.*]], i64
%[[VAR]])
+// CHECK-IR-NEXT: call void @llvm.aarch64.sys(i32 0, i32 7, i32 5, i32 0, i64
%[[VAR]])
__sys(ARM64_AT_S1E2W, v);
-// CHECK-ASM: msr S1_4_C7_C8_1, x8
+// CHECK-ASM: at s1e2w, x8
// CHECK-IR: %[[VAR:.*]] = load i64,
-// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD4:.*]], i64
%[[VAR]])
+// CHECK-IR-NEXT: call void @llvm.aarch64.sys(i32 4, i32 7, i32 8, i32 1, i64
%[[VAR]])
__sys(ARM64_TLBI_VMALLE1, v);
-// CHECK-ASM: msr S1_0_C8_C7_0, x8
+// CHECK-ASM: sys #0, c8, c7, #0, x8
// CHECK-IR: %[[VAR:.*]] = load i64,
-// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD5:.*]], i64
%[[VAR]])
+// CHECK-IR-NEXT: call void @llvm.aarch64.sys(i32 0, i32 8, i32 7, i32 0, i64
%[[VAR]])
__sys(ARM64_CFP_RCTX, v);
-// CHECK-ASM: msr S1_3_C7_C3_4, x8
+// CHECK-ASM: sys #3, c7, c3, #4, x8
// CHECK-IR: %[[VAR:.*]] = load i64,
-// CHECK-IR-NEXT: call void @llvm.write_register.i64(metadata ![[MD6:.*]], i64
%[[VAR]])
+// CHECK-IR-NEXT: call void @llvm.aarch64.sys(i32 3, i32 7, i32 3, i32 4, i64
%[[VAR]])
}
-
----------------
dpaoliello wrote:
Can we please add tests that using `0` for the last parameter (e.g.,
`__sys(ARM64_TLBI_VMALLE1, 0)`) results in `xzr`?
Per the [Arm64
docs](https://developer.arm.com/documentation/ddi0601/2025-12/AArch64-Instructions/TLBI-VMALLE1--TLBI-VMALLE1NXS--TLB-Invalidate-by-VMID--All-at-stage-1--EL1?lang=en):
> Executing TLBI VMALLE1, TLBI VMALLE1NXS
The Rt field should be set to 0b11111. If the Rt field is not set to 0b11111,
it is CONSTRAINED UNPREDICTABLE whether:
> * The instruction is UNDEFINED.
> * The instruction behaves as if the Rt field is set to 0b11111.
'0b11111' is `xzr`.
https://github.com/llvm/llvm-project/pull/187290
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