https://github.com/jam7 updated https://github.com/llvm/llvm-project/pull/186587
>From ad173e83d789313d69983f7db143a3f2eb810960 Mon Sep 17 00:00:00 2001 From: "Kazushi (Jam) Marukawa" <[email protected]> Date: Sat, 21 Feb 2026 04:34:41 +0900 Subject: [PATCH 1/2] [VE] Enable _BitInt support Add hasBitIntType() override returning true in VETargetInfo in order to enable _BitInt for VE. --- clang/lib/Basic/Targets/VE.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/clang/lib/Basic/Targets/VE.h b/clang/lib/Basic/Targets/VE.h index b518407d34438..17ea07541420f 100644 --- a/clang/lib/Basic/Targets/VE.h +++ b/clang/lib/Basic/Targets/VE.h @@ -53,6 +53,8 @@ class LLVM_LIBRARY_VISIBILITY VETargetInfo : public TargetInfo { bool hasSjLjLowering() const override { return true; } + bool hasBitIntType() const override { return true; } + llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override; BuiltinVaListKind getBuiltinVaListKind() const override { >From 692f17d728fedacc3e2a359026a6847a4336efe6 Mon Sep 17 00:00:00 2001 From: "Kazushi (Jam) Marukawa" <[email protected]> Date: Thu, 19 Mar 2026 17:34:27 +0900 Subject: [PATCH 2/2] [VE] Add _BitInt codegen tests Add tests for _BitInt support on VE: - clang/test/CodeGen/VE/bitint.c: Clang IR generation test for _BitInt addition with various widths (i17, i32, i65, i77) and signedness. - llvm/test/CodeGen/VE/Scalar/bitint_addition.ll: LLVM CodeGen test for non-power-of-2 integer addition (i17, i65, i77). - llvm/test/CodeGen/VE/Scalar/bitint_cast.ll: LLVM CodeGen test for trunc/sext/zext between non-power-of-2 and standard integer types. --- clang/test/CodeGen/VE/bitint.c | 92 +++++++++++++++++++ .../test/CodeGen/VE/Scalar/bitint_addition.ll | 52 +++++++++++ llvm/test/CodeGen/VE/Scalar/bitint_cast.ll | 73 +++++++++++++++ 3 files changed, 217 insertions(+) create mode 100644 clang/test/CodeGen/VE/bitint.c create mode 100644 llvm/test/CodeGen/VE/Scalar/bitint_addition.ll create mode 100644 llvm/test/CodeGen/VE/Scalar/bitint_cast.ll diff --git a/clang/test/CodeGen/VE/bitint.c b/clang/test/CodeGen/VE/bitint.c new file mode 100644 index 0000000000000..3b1eb5577e48e --- /dev/null +++ b/clang/test/CodeGen/VE/bitint.c @@ -0,0 +1,92 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature +// RUN: %clang_cc1 -triple ve-unknown-linux -O2 -emit-llvm -o - %s | FileCheck %s + +// CHECK-LABEL: define {{[^@]+}}@test_bitint_17_add_unsigned +// CHECK-SAME: (i17 noundef zeroext [[A:%.*]], i17 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[ADD:%.*]] = add i17 [[B]], [[A]] +// CHECK-NEXT: ret i17 [[ADD]] +// +unsigned _BitInt(17) test_bitint_17_add_unsigned(unsigned _BitInt(17) a, unsigned _BitInt(17) b) { + return a + b; +} + +// CHECK-LABEL: define {{[^@]+}}@test_bitint_17_add_signed +// CHECK-SAME: (i17 noundef signext [[A:%.*]], i17 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[ADD:%.*]] = add nsw i17 [[B]], [[A]] +// CHECK-NEXT: ret i17 [[ADD]] +// +signed _BitInt(17) test_bitint_17_add_signed(signed _BitInt(17) a, signed _BitInt(17) b) { + return a + b; +} + +// CHECK-LABEL: define {{[^@]+}}@test_bitint_17_add_default +// CHECK-SAME: (i17 noundef signext [[A:%.*]], i17 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[ADD:%.*]] = add nsw i17 [[B]], [[A]] +// CHECK-NEXT: ret i17 [[ADD]] +// +_BitInt(17) test_bitint_17_add_default(_BitInt(17) a, _BitInt(17) b) { + return a + b; +} + +// CHECK-LABEL: define {{[^@]+}}@test_bitint_32_add_unsigned +// CHECK-SAME: (i32 noundef zeroext [[A:%.*]], i32 noundef zeroext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[ADD:%.*]] = add i32 [[B]], [[A]] +// CHECK-NEXT: ret i32 [[ADD]] +// +unsigned _BitInt(32) test_bitint_32_add_unsigned(unsigned _BitInt(32) a, unsigned _BitInt(32) b) { + return a + b; +} + +// CHECK-LABEL: define {{[^@]+}}@test_bitint_32_add_signed +// CHECK-SAME: (i32 noundef signext [[A:%.*]], i32 noundef signext [[B:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[B]], [[A]] +// CHECK-NEXT: ret i32 [[ADD]] +// +signed _BitInt(32) test_bitint_32_add_signed(signed _BitInt(32) a, signed _BitInt(32) b) { + return a + b; +} + +// CHECK-LABEL: define {{[^@]+}}@test_bitint_65_add_unsigned +// CHECK-SAME: (i65 noundef [[A:%.*]], i65 noundef [[B:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[ADD:%.*]] = add i65 [[B]], [[A]] +// CHECK-NEXT: ret i65 [[ADD]] +// +unsigned _BitInt(65) test_bitint_65_add_unsigned(unsigned _BitInt(65) a, unsigned _BitInt(65) b) { + return a + b; +} + +// CHECK-LABEL: define {{[^@]+}}@test_bitint_65_add_signed +// CHECK-SAME: (i65 noundef [[A:%.*]], i65 noundef [[B:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[ADD:%.*]] = add nsw i65 [[B]], [[A]] +// CHECK-NEXT: ret i65 [[ADD]] +// +signed _BitInt(65) test_bitint_65_add_signed(signed _BitInt(65) a, signed _BitInt(65) b) { + return a + b; +} + +// CHECK-LABEL: define {{[^@]+}}@test_bitint_77_add_unsigned +// CHECK-SAME: (i77 noundef [[A:%.*]], i77 noundef [[B:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[ADD:%.*]] = add i77 [[B]], [[A]] +// CHECK-NEXT: ret i77 [[ADD]] +// +unsigned _BitInt(77) test_bitint_77_add_unsigned(unsigned _BitInt(77) a, unsigned _BitInt(77) b) { + return a + b; +} + +// CHECK-LABEL: define {{[^@]+}}@test_bitint_77_add_signed +// CHECK-SAME: (i77 noundef [[A:%.*]], i77 noundef [[B:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[ADD:%.*]] = add nsw i77 [[B]], [[A]] +// CHECK-NEXT: ret i77 [[ADD]] +// +signed _BitInt(77) test_bitint_77_add_signed(signed _BitInt(77) a, signed _BitInt(77) b) { + return a + b; +} diff --git a/llvm/test/CodeGen/VE/Scalar/bitint_addition.ll b/llvm/test/CodeGen/VE/Scalar/bitint_addition.ll new file mode 100644 index 0000000000000..44acaca76c199 --- /dev/null +++ b/llvm/test/CodeGen/VE/Scalar/bitint_addition.ll @@ -0,0 +1,52 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define zeroext i17 @add_i17_zext(i17 zeroext %0, i17 zeroext %1) { +; CHECK-LABEL: add_i17_zext: +; CHECK: # %bb.0: +; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 +; CHECK-NEXT: and %s0, %s0, (47)0 +; CHECK-NEXT: b.l.t (, %s10) + %3 = add i17 %1, %0 + ret i17 %3 +} + +define signext i17 @add_i17_sext(i17 signext %0, i17 signext %1) { +; CHECK-LABEL: add_i17_sext: +; CHECK: # %bb.0: +; CHECK-NEXT: adds.w.sx %s0, %s1, %s0 +; CHECK-NEXT: sll %s0, %s0, 47 +; CHECK-NEXT: sra.l %s0, %s0, 47 +; CHECK-NEXT: b.l.t (, %s10) + %3 = add nsw i17 %1, %0 + ret i17 %3 +} + +define i65 @add_i65(i65 %0, i65 %1) { +; CHECK-LABEL: add_i65: +; CHECK: # %bb.0: +; CHECK-NEXT: adds.l %s1, %s3, %s1 +; CHECK-NEXT: adds.l %s0, %s2, %s0 +; CHECK-NEXT: cmpu.l %s2, %s0, %s2 +; CHECK-NEXT: or %s3, 0, (0)1 +; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s2 +; CHECK-NEXT: adds.w.zx %s2, %s3, (0)1 +; CHECK-NEXT: adds.l %s1, %s1, %s2 +; CHECK-NEXT: b.l.t (, %s10) + %3 = add i65 %1, %0 + ret i65 %3 +} + +define i77 @add_i77(i77 %0, i77 %1) { +; CHECK-LABEL: add_i77: +; CHECK: # %bb.0: +; CHECK-NEXT: adds.l %s1, %s3, %s1 +; CHECK-NEXT: adds.l %s0, %s2, %s0 +; CHECK-NEXT: cmpu.l %s2, %s0, %s2 +; CHECK-NEXT: or %s3, 0, (0)1 +; CHECK-NEXT: cmov.l.lt %s3, (63)0, %s2 +; CHECK-NEXT: adds.w.zx %s2, %s3, (0)1 +; CHECK-NEXT: adds.l %s1, %s1, %s2 +; CHECK-NEXT: b.l.t (, %s10) + %3 = add i77 %1, %0 + ret i77 %3 +} diff --git a/llvm/test/CodeGen/VE/Scalar/bitint_cast.ll b/llvm/test/CodeGen/VE/Scalar/bitint_cast.ll new file mode 100644 index 0000000000000..99aecb84bcbc9 --- /dev/null +++ b/llvm/test/CodeGen/VE/Scalar/bitint_cast.ll @@ -0,0 +1,73 @@ +; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s + +define signext i32 @trunc_i65_to_i32(i65 %0) { +; CHECK-LABEL: trunc_i65_to_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: adds.w.sx %s0, %s0, (0)1 +; CHECK-NEXT: b.l.t (, %s10) + %2 = trunc i65 %0 to i32 + ret i32 %2 +} + +define i65 @sext_i32_to_i65(i32 signext %0) { +; CHECK-LABEL: sext_i32_to_i65: +; CHECK: # %bb.0: +; CHECK-NEXT: sra.l %s1, %s0, 63 +; CHECK-NEXT: b.l.t (, %s10) + %2 = sext i32 %0 to i65 + ret i65 %2 +} + +define i65 @zext_i32_to_i65(i32 zeroext %0) { +; CHECK-LABEL: zext_i32_to_i65: +; CHECK: # %bb.0: +; CHECK-NEXT: or %s1, 0, (0)1 +; CHECK-NEXT: b.l.t (, %s10) + %2 = zext i32 %0 to i65 + ret i65 %2 +} + +define signext i17 @trunc_i64_to_i17(i64 %0) { +; CHECK-LABEL: trunc_i64_to_i17: +; CHECK: # %bb.0: +; CHECK-NEXT: sll %s0, %s0, 47 +; CHECK-NEXT: sra.l %s0, %s0, 47 +; CHECK-NEXT: b.l.t (, %s10) + %2 = trunc i64 %0 to i17 + ret i17 %2 +} + +define i64 @sext_i17_to_i64(i17 signext %0) { +; CHECK-LABEL: sext_i17_to_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) + %2 = sext i17 %0 to i64 + ret i64 %2 +} + +define i64 @zext_i17_to_i64(i17 zeroext %0) { +; CHECK-LABEL: zext_i17_to_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: b.l.t (, %s10) + %2 = zext i17 %0 to i64 + ret i64 %2 +} + +define i128 @sext_i77_to_i128(i77 %0) { +; CHECK-LABEL: sext_i77_to_i128: +; CHECK: # %bb.0: +; CHECK-NEXT: sll %s1, %s1, 51 +; CHECK-NEXT: sra.l %s1, %s1, 51 +; CHECK-NEXT: b.l.t (, %s10) + %2 = sext i77 %0 to i128 + ret i128 %2 +} + +define i128 @zext_i77_to_i128(i77 %0) { +; CHECK-LABEL: zext_i77_to_i128: +; CHECK: # %bb.0: +; CHECK-NEXT: and %s1, %s1, (51)0 +; CHECK-NEXT: b.l.t (, %s10) + %2 = zext i77 %0 to i128 + ret i128 %2 +} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
