================
@@ -1729,6 +1729,27 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr
*MI) {
EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::EnforceIEIO));
return;
}
+ case PPC::BL8:
+ case PPC::BL8_NOP: {
+ const MachineOperand &MO = MI->getOperand(0);
+ if (MO.isSymbol()) {
+ StringRef Name = MO.getSymbolName();
+ Name.consume_front(".");
+ Name.consume_back("[PR]");
+ bool IsLWAT = Name == "__lwat_csne_pseudo";
+ bool IsLDAT = Name == "__ldat_csne_pseudo";
+ if (IsLWAT || IsLDAT) {
----------------
nikic wrote:
I'm not sure I follow. It looks like the registers are fixed here, so why does
this need a new register class? Wouldn't it be sufficient to mark x4 and x5 as
implicit-def for the instruction?
https://github.com/llvm/llvm-project/pull/178061
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