Author: Craig Topper Date: 2026-03-24T11:48:55-07:00 New Revision: 5928fc42d8e8d4992266602eaf44210a2c530253
URL: https://github.com/llvm/llvm-project/commit/5928fc42d8e8d4992266602eaf44210a2c530253 DIFF: https://github.com/llvm/llvm-project/commit/5928fc42d8e8d4992266602eaf44210a2c530253.diff LOG: [RISCV] Use uimm3/4/5/6_plus1 for (P)SATI instructions. (#186541) The encoded immediate is the number of trailing 1s in the maximum value. Mailing list discussion has a preference to print and parse this value plus one. https://lists.riscv.org/g/tech-p-ext/message/910 With this patch, saturating to a signed 8-bit integer would be "sati a0, a0, 8". Previously it was "sati a0, a0, 7". This is reflected in version 0.20 of the adoc spec here https://github.com/riscv/riscv-p-spec/pull/226. I have updated our RISCVUsage.rst to point to the adoc version of the spec. Added: Modified: clang/test/Driver/print-supported-extensions-riscv.c clang/test/Preprocessor/riscv-target-features.c llvm/docs/RISCVUsage.rst llvm/docs/ReleaseNotes.md llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h llvm/lib/Target/RISCV/RISCVFeatures.td llvm/lib/Target/RISCV/RISCVInstrInfoP.td llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td llvm/test/CodeGen/RISCV/attributes.ll llvm/test/MC/RISCV/attribute-arch.s llvm/test/MC/RISCV/rv32p-invalid.s llvm/test/MC/RISCV/rv32p-valid.s llvm/test/MC/RISCV/rv64p-invalid.s llvm/test/MC/RISCV/rv64p-valid.s llvm/unittests/TargetParser/RISCVISAInfoTest.cpp Removed: ################################################################################ diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index b0e82b08f07e0..f9d1bfa2c2059 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -241,7 +241,7 @@ // CHECK-NEXT: xwchc 2.2 'Xwchc' (WCH/QingKe additional compressed opcodes) // CHECK-EMPTY: // CHECK-NEXT: Experimental extensions -// CHECK-NEXT: p 0.19 'P' ('Base P' (Packed SIMD)) +// CHECK-NEXT: p 0.20 'P' ('Base P' (Packed SIMD)) // CHECK-NEXT: y 0.96 'Y' ('Base Y' (CHERI)) // CHECK-NEXT: zibi 0.1 'Zibi' (Branch with Immediate) // CHECK-NEXT: zicfilp 1.0 'Zicfilp' (Landing pad) diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 863ff3f08a9ea..1c8018c57ece2 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -180,6 +180,7 @@ // Experimental extensions +// CHECK-NOT: __riscv_p {{.*$}} // CHECK-NOT: __riscv_zicfilp {{.*$}} // CHECK-NOT: __riscv_zicfiss {{.*$}} // CHECK-NOT: __riscv_zvbc32e {{.*$}} @@ -1583,6 +1584,15 @@ // CHECK-ZVKT-EXT: __riscv_zvkt 1000000{{$}} // Experimental extensions + +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_p0p20 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_p0p20 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-P-EXT %s +// CHECK-P-EXT: __riscv_p 20000{{$}} +// // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32izfbfmin1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZFBFMIN-EXT %s diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index b6d3950c56ceb..860c9b67f548f 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -336,7 +336,7 @@ LLVM supports (to various degrees) a number of experimental extensions. All exp The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised. ``experimental-p`` - LLVM implements the `019 draft specification <https://www.jhauser.us/RISCV/ext-P/>`__. + LLVM implements the `0.20 draft specification <https://github.com/riscv/riscv-p-spec/blob/master/P-ext-proposal.adoc>`__. ``experimental-zibi`` LLVM implements the `0.1 release specification <https://github.com/riscv/zibi/releases/tag/v0.1.0>`__. diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index 249ddc27fb3ea..e26d5acb601e1 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -167,7 +167,7 @@ Changes to the RISC-V Backend * `llvm-objdump` now has support for `--symbolize-operands` with RISC-V. * `-mcpu=spacemit-x100` was added. -* Change P extension version to match the 019 draft specification. Encoded in `-march` as `0p19`. +* Change P extension version to match the 0.20 draft specification. * Mnemonics for MOP/HINT-based instructions (`lpad`, `pause`, `ntl.*`, `c.ntl.*`, `sspush`, `sspopchk`, `ssrdp`, `c.sspush`, `c.sspopchk`) are now always available in the assembler and disassembler without requiring their respective diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 9bf3bb4bdcaa0..0d9b9b06f9973 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -749,11 +749,21 @@ struct RISCVOperand final : public MCParsedAsmOperand { return isUImmPred([](int64_t Imm) { return isUInt<5>(Imm) && Imm > 3; }); } + bool isUImm4Plus1() const { + return isUImmPred( + [](int64_t Imm) { return Imm > 0 && isUInt<4>(Imm - 1); }); + } + bool isUImm5Plus1() const { return isUImmPred( [](int64_t Imm) { return Imm > 0 && isUInt<5>(Imm - 1); }); } + bool isUImm6Plus1() const { + return isUImmPred( + [](int64_t Imm) { return Imm > 0 && isUInt<6>(Imm - 1); }); + } + bool isUImm5GE6Plus1() const { return isUImmPred( [](int64_t Imm) { return Imm >= 6 && isUInt<5>(Imm - 1); }); @@ -1512,6 +1522,8 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 3) - 1); case Match_InvalidUImm4: return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 4) - 1); + case Match_InvalidUImm4Plus1: + return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 4)); case Match_InvalidUImm5: return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 5) - 1); case Match_InvalidUImm5NonZero: @@ -1529,6 +1541,8 @@ bool RISCVAsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, } case Match_InvalidUImm6: return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 6) - 1); + case Match_InvalidUImm6Plus1: + return generateImmOutOfRangeError(Operands, ErrorInfo, 1, (1 << 6)); case Match_InvalidUImm7: return generateImmOutOfRangeError(Operands, ErrorInfo, 0, (1 << 7) - 1); case Match_InvalidUImm8: diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index c4d54bdd60737..b5aade96d4093 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -33,6 +33,7 @@ enum OperandType : unsigned { OPERAND_UIMM2_LSB0, OPERAND_UIMM3, OPERAND_UIMM4, + OPERAND_UIMM4_PLUS1, OPERAND_UIMM5, OPERAND_UIMM5_NONZERO, OPERAND_UIMM5_GT3, @@ -41,6 +42,7 @@ enum OperandType : unsigned { OPERAND_UIMM5_LSB0, OPERAND_UIMM5_SLIST, OPERAND_UIMM6, + OPERAND_UIMM6_PLUS1, OPERAND_UIMM6_LSB0, OPERAND_UIMM7, OPERAND_UIMM7_LSB00, diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 01ab6054c5e64..afd3f3d3380cd 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1114,7 +1114,7 @@ def HasStdExtSmctrOrSsctr : Predicate<"Subtarget->hasStdExtSmctrOrSsctr()">, // Packed SIMD Extensions def FeatureStdExtP - : RISCVExperimentalExtension<0, 19, + : RISCVExperimentalExtension<0, 20, "'Base P' (Packed SIMD)", [FeatureStdExtZmmul, FeatureStdExtZba, FeatureStdExtZbb, FeatureStdExtZicsr]>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td index 788ecda2a1df1..826abfa689682 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoP.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoP.td @@ -105,6 +105,30 @@ def simm10_pli_w : RISCVOp { }]; } +class UImmPlus1AsmOperand<int width> : AsmOperandClass { + let Name = "UImm" # width # "Plus1"; + let RenderMethod = "addImmOperands"; + let DiagnosticType = "InvalidUImm" # width # "Plus1"; +} + +class RISCVUImmPlus1Op<int bitsNum> + : RISCVOp, ImmLeaf<XLenVT, "return Imm > 0 && isUInt<" # bitsNum # ">(Imm - 1);"> { + let ParserMatchClass = UImmPlus1AsmOperand<bitsNum>; + let EncoderMethod = "getImmOpValueMinus1"; + let DecoderMethod = "decodeUImmPlus1Operand<" # bitsNum # ">"; + let OperandType = "OPERAND_UIMM" # bitsNum # "_PLUS1"; + let MCOperandPredicate = [{ + int64_t Imm; + if (!MCOp.evaluateAsConstantImm(Imm)) + return false; + return Imm > 0 && isUInt<}] # bitsNum # [{>(Imm - 1); + }]; +} + +def uimm4_plus1 : RISCVUImmPlus1Op<4>; +def uimm5_plus1 : RISCVUImmPlus1Op<5>; +def uimm6_plus1 : RISCVUImmPlus1Op<6>; + //===----------------------------------------------------------------------===// // Instruction class templates //===----------------------------------------------------------------------===// @@ -220,32 +244,36 @@ class RVPShift_ri<bits<3> f, bits<3> funct3, string opcodestr, Operand ImmType> let Inst{27} = 0b0; } -class RVPShiftD_ri<bits<3> f, bits<3> funct3, string opcodestr> - : RVPShift_ri<f, funct3, opcodestr, uimm6> { +class RVPShiftD_ri<bits<3> f, bits<3> funct3, string opcodestr, + Operand ImmType = uimm6> + : RVPShift_ri<f, funct3, opcodestr, ImmType> { bits<6> shamt; let Inst{26} = 0b1; let Inst{25-20} = shamt; } -class RVPShiftW_ri<bits<3> f, bits<3> funct3, string opcodestr> - : RVPShift_ri<f, funct3, opcodestr, uimm5> { +class RVPShiftW_ri<bits<3> f, bits<3> funct3, string opcodestr, + Operand ImmType = uimm5> + : RVPShift_ri<f, funct3, opcodestr, ImmType> { bits<5> shamt; let Inst{26-25} = 0b01; let Inst{24-20} = shamt; } -class RVPShiftH_ri<bits<3> f, bits<3> funct3, string opcodestr> - : RVPShift_ri<f, funct3, opcodestr, uimm4> { +class RVPShiftH_ri<bits<3> f, bits<3> funct3, string opcodestr, + Operand ImmType = uimm4> + : RVPShift_ri<f, funct3, opcodestr, ImmType> { bits<4> shamt; let Inst{26-24} = 0b001; let Inst{23-20} = shamt; } -class RVPShiftB_ri<bits<3> f, bits<3> funct3, string opcodestr> - : RVPShift_ri<f, funct3, opcodestr, uimm3> { +class RVPShiftB_ri<bits<3> f, bits<3> funct3, string opcodestr, + Operand ImmType = uimm3> + : RVPShift_ri<f, funct3, opcodestr, ImmType> { bits<3> shamt; let Inst{26-23} = 0b0001; @@ -636,7 +664,7 @@ let Predicates = [HasStdExtP] in { def PSRARI_H : RVPShiftH_ri<0b101, 0b100, "psrari.h">; let Defs = [VXSAT] in - def PSATI_H : RVPShiftH_ri<0b110, 0b100, "psati.h">; + def PSATI_H : RVPShiftH_ri<0b110, 0b100, "psati.h", uimm4_plus1>; } // Predicates = [HasStdExtP] let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in { let Defs = [VXSAT] in @@ -645,7 +673,7 @@ let Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" in { def SRARI_RV32 : RVPShiftW_ri<0b101, 0b100, "srari">; let Defs = [VXSAT] in - def SATI_RV32 : RVPShiftW_ri<0b110, 0b100, "sati">; + def SATI_RV32 : RVPShiftW_ri<0b110, 0b100, "sati", uimm5_plus1>; } // Predicates = [HasStdExtP, IsRV32], DecoderNamespace = "RV32Only" let Predicates = [HasStdExtP, IsRV64] in { def PSRLI_W : RVPShiftW_ri<0b000, 0b100, "psrli.w">; @@ -660,8 +688,8 @@ let Predicates = [HasStdExtP, IsRV64] in { def SRARI_RV64 : RVPShiftD_ri<0b101, 0b100, "srari">; let Defs = [VXSAT] in { - def PSATI_W : RVPShiftW_ri<0b110, 0b100, "psati.w">; - def SATI_RV64 : RVPShiftD_ri<0b110, 0b100, "sati">; + def PSATI_W : RVPShiftW_ri<0b110, 0b100, "psati.w", uimm5_plus1>; + def SATI_RV64 : RVPShiftD_ri<0b110, 0b100, "sati", uimm6_plus1>; } // Defs = [VXSAT] } // Predicates = [HasStdExtP, IsRV64] diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td index f944b703eb806..d868a7aa80d38 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td @@ -55,26 +55,6 @@ def uimm5gt3 : RISCVOp<XLenVT>, ImmLeaf<XLenVT, def tuimm5gt3 : TImmLeaf<XLenVT, [{return (Imm > 3) && isUInt<5>(Imm);}]>; -def UImm5Plus1AsmOperand : AsmOperandClass { - let Name = "UImm5Plus1"; - let RenderMethod = "addImmOperands"; - let DiagnosticType = "InvalidUImm5Plus1"; -} - -def uimm5_plus1 : RISCVOp, ImmLeaf<XLenVT, - [{return Imm >= 1 && Imm <= 32;}]> { - let ParserMatchClass = UImm5Plus1AsmOperand; - let EncoderMethod = "getImmOpValueMinus1"; - let DecoderMethod = "decodeUImmPlus1Operand<5>"; - let OperandType = "OPERAND_UIMM5_PLUS1"; - let MCOperandPredicate = [{ - int64_t Imm; - if (!MCOp.evaluateAsConstantImm(Imm)) - return false; - return Imm >= 1 && Imm <= 32; - }]; -} - def uimm5ge6_plus1 : RISCVOp<XLenVT>, ImmLeaf<XLenVT, [{return Imm >= 6 && Imm <= 32;}]> { let ParserMatchClass = UImmAsmOperand<5, "GE6Plus1">; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 3cac9c56503a9..2f0e35d339f01 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -626,7 +626,7 @@ ; RV64SSCTR: .attribute 5, "rv64i2p1_sscsrind1p0_ssctr1p0" ; RV64SDEXT: .attribute 5, "rv64i2p1_sdext1p0" ; RV64SDTRIG: .attribute 5, "rv64i2p1_sdtrig1p0" -; RV64P: .attribute 5, "rv64i2p1_p0p19_zicsr2p0_zmmul1p0_zba1p0_zbb1p0" +; RV64P: .attribute 5, "rv64i2p1_p0p20_zicsr2p0_zmmul1p0_zba1p0_zbb1p0" ; RV64Y: .attribute 5, "rv64i2p1_y0p96" ; RV64ZIBI: .attribute 5, "rv64i2p1_zibi0p1" diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 1ad595b28efaa..7d49558295cb3 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -510,8 +510,8 @@ .attribute arch, "rv32i_sdtrig1p0" # CHECK: attribute 5, "rv32i2p1_sdtrig1p0" -.attribute arch, "rv32i_p0p19" -# CHECK: attribute 5, "rv32i2p1_p0p19_zicsr2p0_zmmul1p0_zba1p0_zbb1p0" +.attribute arch, "rv32i_p0p20" +# CHECK: attribute 5, "rv32i2p1_p0p20_zicsr2p0_zmmul1p0_zba1p0_zbb1p0" -.attribute arch, "rv64i_p0p19" -# CHECK: attribute 5, "rv64i2p1_p0p19_zicsr2p0_zmmul1p0_zba1p0_zbb1p0" +.attribute arch, "rv64i_p0p20" +# CHECK: attribute 5, "rv64i2p1_p0p20_zicsr2p0_zmmul1p0_zba1p0_zbb1p0" diff --git a/llvm/test/MC/RISCV/rv32p-invalid.s b/llvm/test/MC/RISCV/rv32p-invalid.s index 105444cf6b300..6ff44b9dc4fe0 100644 --- a/llvm/test/MC/RISCV/rv32p-invalid.s +++ b/llvm/test/MC/RISCV/rv32p-invalid.s @@ -37,9 +37,9 @@ psrari.h ra, sp, 100 # CHECK: :[[@LINE]]:18: error: immediate must be an integer psrari.w ra, sp, 15 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set srari ra, sp, 100 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 31] -psati.h ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 15] +psati.h ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [1, 16] psati.w ra, sp, 24 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set -sati ra, sp, 100 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 31] +sati ra, sp, 100 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [1, 32] psrl.ws a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set predsum.ws a0, a1, a2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instruction Set diff --git a/llvm/test/MC/RISCV/rv32p-valid.s b/llvm/test/MC/RISCV/rv32p-valid.s index a37669086c67b..9729fd6610147 100644 --- a/llvm/test/MC/RISCV/rv32p-valid.s +++ b/llvm/test/MC/RISCV/rv32p-valid.s @@ -109,12 +109,12 @@ psrari.h t4, t5, 6 # CHECK-ASM-AND-OBJ: srari t5, t6, 7 # CHECK-ASM: encoding: [0x1b,0xcf,0x7f,0xd2] srari t5, t6, 7 -# CHECK-ASM-AND-OBJ: psati.h t6, s11, 8 +# CHECK-ASM-AND-OBJ: psati.h t6, s11, 9 # CHECK-ASM: encoding: [0x9b,0xcf,0x8d,0xe1] -psati.h t6, s11, 8 -# CHECK-ASM-AND-OBJ: sati s11, s10, 9 +psati.h t6, s11, 9 +# CHECK-ASM-AND-OBJ: sati s11, s10, 10 # CHECK-ASM: encoding: [0x9b,0x4d,0x9d,0xe2] -sati s11, s10, 9 +sati s11, s10, 10 # CHECK-ASM-AND-OBJ: psrl.hs a6, a7, a1 # CHECK-ASM: encoding: [0x1b,0xc8,0xb8,0x88] psrl.hs a6, a7, a1 diff --git a/llvm/test/MC/RISCV/rv64p-invalid.s b/llvm/test/MC/RISCV/rv64p-invalid.s index e18c9ec0e29ea..434abf54be3da 100644 --- a/llvm/test/MC/RISCV/rv64p-invalid.s +++ b/llvm/test/MC/RISCV/rv64p-invalid.s @@ -33,9 +33,9 @@ psrari.h ra, sp, 100 # CHECK: :[[@LINE]]:18: error: immediate must be an integer psrari.w ra, sp, 100 # CHECK: :[[@LINE]]:18: error: immediate must be an integer in the range [0, 31] srari ra, sp, 100 # CHECK: :[[@LINE]]:15: error: immediate must be an integer in the range [0, 63] -psati.h ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 15] -psati.w ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [0, 31] -sati ra, sp, 100 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [0, 63] +psati.h ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [1, 16] +psati.w ra, sp, 100 # CHECK: :[[@LINE]]:17: error: immediate must be an integer in the range [1, 32] +sati ra, sp, 100 # CHECK: :[[@LINE]]:14: error: immediate must be an integer in the range [1, 64] sadd t1, a7, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set aadd t1, a7, a0 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV32I Base Instruction Set diff --git a/llvm/test/MC/RISCV/rv64p-valid.s b/llvm/test/MC/RISCV/rv64p-valid.s index bb96b067c448c..7d91057327117 100644 --- a/llvm/test/MC/RISCV/rv64p-valid.s +++ b/llvm/test/MC/RISCV/rv64p-valid.s @@ -160,15 +160,15 @@ psrari.w t5, t6, 7 # CHECK-ASM-AND-OBJ: srari t6, s11, 63 # CHECK-ASM: encoding: [0x9b,0xcf,0xfd,0xd7] srari t6, s11, 63 -# CHECK-ASM-AND-OBJ: psati.h s11, s10, 9 +# CHECK-ASM-AND-OBJ: psati.h s11, s10, 10 # CHECK-ASM: encoding: [0x9b,0x4d,0x9d,0xe1] -psati.h s11, s10, 9 -# CHECK-ASM-AND-OBJ: psati.w s10, s9, 10 +psati.h s11, s10, 10 +# CHECK-ASM-AND-OBJ: psati.w s10, s9, 11 # CHECK-ASM: encoding: [0x1b,0xcd,0xac,0xe2] -psati.w s10, s9, 10 -# CHECK-ASM-AND-OBJ: sati s9, s8, 32 +psati.w s10, s9, 11 +# CHECK-ASM-AND-OBJ: sati s9, s8, 33 # CHECK-ASM: encoding: [0x9b,0x4c,0x0c,0xe6] -sati s9, s8, 32 +sati s9, s8, 33 # CHECK-ASM-AND-OBJ: psrl.hs a6, a7, a1 # CHECK-ASM: encoding: [0x1b,0xc8,0xb8,0x88] psrl.hs a6, a7, a1 diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 89efc4734f35b..38efdb87ee88a 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1372,7 +1372,7 @@ R"(All available -march extensions for RISC-V xwchc 2.2 Experimental extensions - p 0.19 + p 0.20 y 0.96 zibi 0.1 zicfilp 1.0 This is a long dummy description _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
