https://github.com/kkwli created https://github.com/llvm/llvm-project/pull/188343
This patch is to align with how clang sets up the target features for PowerPC in order to benefit the inlining in LTO. Previous PR: https://github.com/llvm/llvm-project/pull/169860 >From adf606fcb84c46fdbb279914e0ebcb64900bf07f Mon Sep 17 00:00:00 2001 From: Kelvin Li <[email protected]> Date: Tue, 24 Mar 2026 12:28:34 -0400 Subject: [PATCH] [flang][PPC] Set PPC default target features This patch is to align with how clang sets up the target features for PowerPC in order to benefit the inlining in LTO. --- clang/lib/Driver/ToolChains/Flang.cpp | 1 + flang/lib/Frontend/CompilerInstance.cpp | 29 ++++++++++++++++++++++++ flang/test/Lower/target-features-ppc.f90 | 15 ++++++++++++ 3 files changed, 45 insertions(+) create mode 100644 flang/test/Lower/target-features-ppc.f90 diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index d56a8c4448469..8507a5990adb7 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -614,6 +614,7 @@ void Flang::addTargetOptions(const ArgList &Args, case llvm::Triple::ppc: case llvm::Triple::ppc64: case llvm::Triple::ppc64le: + getTargetFeatures(D, Triple, Args, CmdArgs, /*ForAs*/ false); AddPPCTargetArgs(Args, CmdArgs); break; case llvm::Triple::loongarch64: diff --git a/flang/lib/Frontend/CompilerInstance.cpp b/flang/lib/Frontend/CompilerInstance.cpp index 5448293584d47..82395c14acac6 100644 --- a/flang/lib/Frontend/CompilerInstance.cpp +++ b/flang/lib/Frontend/CompilerInstance.cpp @@ -28,6 +28,7 @@ #include "llvm/Support/FileSystem.h" #include "llvm/Support/Path.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/TargetParser/PPCTargetParser.h" #include "llvm/TargetParser/TargetParser.h" #include "llvm/TargetParser/Triple.h" @@ -309,6 +310,31 @@ getExplicitAndImplicitNVPTXTargetFeatures(clang::DiagnosticsEngine &diags, return llvm::join(featuresVec, ","); } +static std::string +getExplicitAndImplicitPPCTargetFeatures(clang::DiagnosticsEngine &diags, + const TargetOptions &targetOpts, + const llvm::Triple triple, + const CodeGenOptions &CGOpts) { + std::vector<std::string> featuresVec; + std::optional<llvm::StringMap<bool>> FeaturesOpt = + llvm::PPC::getPPCDefaultTargetFeatures(triple, targetOpts.cpu); + if (FeaturesOpt) { + for (auto &I : FeaturesOpt.value()) { + featuresVec.push_back( + (llvm::Twine(I.second ? "+" : "-") + I.first().str()).str()); + } + } + + // Include others set by ppc::getPPCTargetFeatures() and specified by users + for (auto &userFeature : targetOpts.featuresAsWritten) { + llvm::StringRef userKeyString(llvm::StringRef(userFeature).drop_front(1)); + featuresVec.push_back(userFeature[0] + userKeyString.str()); + } + + llvm::sort(featuresVec); + return llvm::join(featuresVec, ","); +} + std::string CompilerInstance::getTargetFeatures() { const TargetOptions &targetOpts = getInvocation().getTargetOpts(); const llvm::Triple triple(targetOpts.triple); @@ -325,6 +351,9 @@ std::string CompilerInstance::getTargetFeatures() { } else if (triple.isNVPTX()) { return getExplicitAndImplicitNVPTXTargetFeatures(getDiagnostics(), targetOpts, triple); + } else if (triple.isPPC()) { + return getExplicitAndImplicitPPCTargetFeatures( + getDiagnostics(), targetOpts, triple, getInvocation().getCodeGenOpts()); } return llvm::join(targetOpts.featuresAsWritten.begin(), targetOpts.featuresAsWritten.end(), ","); diff --git a/flang/test/Lower/target-features-ppc.f90 b/flang/test/Lower/target-features-ppc.f90 new file mode 100644 index 0000000000000..1c3429e6936a0 --- /dev/null +++ b/flang/test/Lower/target-features-ppc.f90 @@ -0,0 +1,15 @@ +! REQUIRES: target=powerpc{{.*}} +! RUN: %flang_fc1 -emit-fir -target-cpu pwr10 %s -o - | FileCheck %s --check-prefixes=ALL,FEATURE +! RUN: %flang_fc1 -emit-fir -target-cpu pwr10 -target-feature +privileged %s -o - | FileCheck %s --check-prefixes=ALL,BOTH + +! ALL: module attributes { + +! ALL: fir.target_cpu = "pwr10" + +! FEATURE: fir.target_features = #llvm.target_features<[ +! FEATURE: "+64bit-support", "+allow-unaligned-fp-access", "+altivec", "+bpermd", "+cmpb", "+crbits", "+crypto", "+direct-move", "+extdiv", "+fast-MFLR", "+fcpsgn", "+fpcvt", "+fprnd", "+fpu", "+fre", "+fres", "+frsqrte", "+frsqrtes", "+fsqrt", "+fuse-add-logical", "+fuse-arith-add", "+fuse-logical", "+fuse-logical-add", "+fuse-sha3", "+fuse-store", "+fusion", "+hard-float", "+icbt", "+isa-v206-instructions", "+isa-v207-instructions", "+isa-v30-instructions", "+isa-v31-instructions", "+isel", "+ldbrx", "+lfiwax", "+mfocrf", "+mma", "+paired-vector-memops", "+partword-atomics", "+pcrelative-memops", "+popcntd", "+power10-vector", "+power8-altivec", "+power8-vector", "+power9-altivec", "+power9-vector", "+ppc-postra-sched", "+ppc-prera-sched", "+predictable-select-expensive", "+prefix-instrs", "+quadword-atomics", "+recipprec", "+stfiwx", "+two-const-nr", "+vsx" +! FEATURE: ]> + +! BOTH: fir.target_features = #llvm.target_features<[ +! BOTH: "+64bit-support", "+allow-unaligned-fp-access", "+altivec", "+bpermd", "+cmpb", "+crbits", "+crypto", "+direct-move", "+extdiv", "+fast-MFLR", "+fcpsgn", "+fpcvt", "+fprnd", "+fpu", "+fre", "+fres", "+frsqrte", "+frsqrtes", "+fsqrt", "+fuse-add-logical", "+fuse-arith-add", "+fuse-logical", "+fuse-logical-add", "+fuse-sha3", "+fuse-store", "+fusion", "+hard-float", "+icbt", "+isa-v206-instructions", "+isa-v207-instructions", "+isa-v30-instructions", "+isa-v31-instructions", "+isel", "+ldbrx", "+lfiwax", "+mfocrf", "+mma", "+paired-vector-memops", "+partword-atomics", "+pcrelative-memops", "+popcntd", "+power10-vector", "+power8-altivec", "+power8-vector", "+power9-altivec", "+power9-vector", "+ppc-postra-sched", "+ppc-prera-sched", "+predictable-select-expensive", "+prefix-instrs", "+privileged", "+quadword-atomics", "+recipprec", "+stfiwx", "+two-const-nr", "+vsx" +! BOTH: ]> _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
