================
@@ -15,22 +15,108 @@
//===------------------------------------------------------===//
// 2.4.1.2. Set all lanes to the same value
-//
-// TODO: Add the remaining intrinsics from this group.
//===------------------------------------------------------===//
// ALL-LABEL: @test_vduph_lane_bf16(
+// LLVM-SAME: <4 x bfloat> {{.*}}[[V:%.*]]) #[[ATTR0:[0-9]+]] {
bfloat16_t test_vduph_lane_bf16(bfloat16x4_t v) {
- // CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !cir.bf16>
- // LLVM: [[VGET_LANE:%.*]] = extractelement <4 x bfloat> %{{.*}}, i32 1
- // LLVM: ret bfloat [[VGET_LANE]]
- return vduph_lane_bf16(v, 1);
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<4 x !cir.bf16>
+
+// LLVM: [[VGET_LANE:%.*]] = extractelement <4 x bfloat> %{{.*}}, i32 1
+// LLVM: ret bfloat [[VGET_LANE]]
+return vduph_lane_bf16(v, 1);
}
// ALL-LABEL: @test_vduph_laneq_bf16(
+// LLVM-SAME: <8 x bfloat> {{.*}}[[V:%.*]]) #[[ATTR0:[0-9]+]] {
bfloat16_t test_vduph_laneq_bf16(bfloat16x8_t v) {
- // CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !cir.bf16>
- // LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x bfloat> %{{.*}}, i32 7
- // LLVM: ret bfloat [[VGETQ_LANE]]
- return vduph_laneq_bf16(v, 7);
+// CIR: cir.vec.extract %{{.*}}[%{{.*}} : !s32i] : !cir.vector<8 x !cir.bf16>
+
+// LLVM: [[VGETQ_LANE:%.*]] = extractelement <8 x bfloat> %{{.*}}, i32 7
+// LLVM: ret bfloat [[VGETQ_LANE]]
+return vduph_laneq_bf16(v, 7);
+}
+
+// ALL-LABEL: @test_vdup_lane_bf16(
+// LLVM-SAME: <4 x bfloat> {{.*}}[[V:%.*]]) #[[ATTR0:[0-9]+]] {
+bfloat16x4_t test_vdup_lane_bf16(bfloat16x4_t v) {
+ // CIR: cir.vec.shuffle({{%.*}}, {{%.*}} : !cir.vector<4 x !cir.bf16>)
[#cir.int<1> : !s32i, #cir.int<1> : !s32i, #cir.int<1> : !s32i, #cir.int<1> :
!s32i] : !cir.vector<4 x !cir.bf16>
+
+ // LLVM: [[TMP0:%.*]] = bitcast <4 x bfloat> [[V]] to <4 x i16>
+ // LLVM: [[TMP1:%.*]] = bitcast <4 x i16> [[TMP0]] to <8 x i8>
+ // LLVM: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x bfloat>
+ // LLVM: [[SHUF:%.*]] = shufflevector <4 x bfloat> [[TMP2]], {{.*}}, <4 x
i{{32|64}}> <i{{32|64}} 1, i{{32|64}} 1, i{{32|64}} 1, i{{32|64}} 1>
----------------
banach-space wrote:
Here and in other places - shouldn't this be `i32`?
```suggestion
// LLVM: [[SHUF:%.*]] = shufflevector <4 x bfloat> [[TMP2]], {{.*}}, <4 x
i32> <i{{32|64}} 1, i{{32|64}} 1, i{{32|64}} 1, i{{32|64}} 1>
```
https://github.com/llvm/llvm-project/pull/187460
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