https://github.com/pau-sum updated https://github.com/llvm/llvm-project/pull/188371
>From 7ae2bc415490ee7a6adc11d1159f3028aa385cb8 Mon Sep 17 00:00:00 2001 From: Pau Sum <[email protected]> Date: Sat, 21 Mar 2026 19:18:58 -0400 Subject: [PATCH 1/4] [CIR][AArch64] Upstream vmull_*/vmull_high_* Neon builtins --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 17 +- clang/test/CodeGen/AArch64/neon-intrinsics.c | 186 --------------- clang/test/CodeGen/AArch64/neon/intrinsics.c | 217 ++++++++++++++++++ 3 files changed, 233 insertions(+), 187 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index a3488bfcc3dec..955d6b677390d 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -2207,7 +2207,22 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, case NEON::BI__builtin_neon_vfmas_laneq_f32: case NEON::BI__builtin_neon_vfmad_lane_f64: case NEON::BI__builtin_neon_vfmad_laneq_f64: - case NEON::BI__builtin_neon_vmull_v: + cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AArch64 builtin call: ") + + getContext().BuiltinInfo.getName(builtinID)); + return mlir::Value{}; + case NEON::BI__builtin_neon_vmull_v: { + intrName = usgn ? "aarch64.neon.umull" : "aarch64.neon.smull"; + if (type.isPoly()) + intrName = "aarch64.neon.pmull"; + // Widening multiply: args have half the element width of the result. + auto resultIntTy = mlir::cast<cir::IntType>(ty.getElementType()); + auto narrowIntTy = + cir::IntType::get(builder.getContext(), resultIntTy.getWidth() / 2, + resultIntTy.isSigned()); + auto argTy = cir::VectorType::get(narrowIntTy, ty.getSize()); + return emitNeonCall(cgm, builder, {argTy, argTy}, ops, intrName, ty, loc); + } case NEON::BI__builtin_neon_vmax_v: case NEON::BI__builtin_neon_vmaxq_v: case NEON::BI__builtin_neon_vmaxh_f16: diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index 8eb6cd86339d6..570343a538ce2 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -11078,170 +11078,6 @@ uint64x2_t test_vabal_high_u32(uint64x2_t a, uint32x4_t b, uint32x4_t c) { return vabal_high_u32(a, b, c); } -// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_s8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]]) -// CHECK-NEXT: ret <8 x i16> [[VMULL_I]] -// -int16x8_t test_vmull_s8(int8x8_t a, int8x8_t b) { - return vmull_s8(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vmull_s16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) -// CHECK-NEXT: ret <4 x i32> [[VMULL2_I]] -// -int32x4_t test_vmull_s16(int16x4_t a, int16x4_t b) { - return vmull_s16(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vmull_s32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) -// CHECK-NEXT: ret <2 x i64> [[VMULL2_I]] -// -int64x2_t test_vmull_s32(int32x2_t a, int32x2_t b) { - return vmull_s32(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_u8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]]) -// CHECK-NEXT: ret <8 x i16> [[VMULL_I]] -// -uint16x8_t test_vmull_u8(uint8x8_t a, uint8x8_t b) { - return vmull_u8(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vmull_u16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) -// CHECK-NEXT: ret <4 x i32> [[VMULL2_I]] -// -uint32x4_t test_vmull_u16(uint16x4_t a, uint16x4_t b) { - return vmull_u16(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vmull_u32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) -// CHECK-NEXT: ret <2 x i64> [[VMULL2_I]] -// -uint64x2_t test_vmull_u32(uint32x2_t a, uint32x2_t b) { - return vmull_u32(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_high_s8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -// CHECK-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[SHUFFLE_I5_I]], <8 x i8> [[SHUFFLE_I_I]]) -// CHECK-NEXT: ret <8 x i16> [[VMULL_I_I]] -// -int16x8_t test_vmull_high_s8(int8x16_t a, int8x16_t b) { - return vmull_high_s8(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vmull_high_s16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7> -// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> [[B]], <4 x i32> <i32 4, i32 5, i32 6, i32 7> -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I5_I]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> -// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]]) -// CHECK-NEXT: ret <4 x i32> [[VMULL2_I_I]] -// -int32x4_t test_vmull_high_s16(int16x8_t a, int16x8_t b) { - return vmull_high_s16(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vmull_high_s32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> <i32 2, i32 3> -// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[B]], <2 x i32> <i32 2, i32 3> -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I5_I]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> -// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]]) -// CHECK-NEXT: ret <2 x i64> [[VMULL2_I_I]] -// -int64x2_t test_vmull_high_s32(int32x4_t a, int32x4_t b) { - return vmull_high_s32(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_high_u8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -// CHECK-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[SHUFFLE_I5_I]], <8 x i8> [[SHUFFLE_I_I]]) -// CHECK-NEXT: ret <8 x i16> [[VMULL_I_I]] -// -uint16x8_t test_vmull_high_u8(uint8x16_t a, uint8x16_t b) { - return vmull_high_u8(a, b); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vmull_high_u16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7> -// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> [[B]], <4 x i32> <i32 4, i32 5, i32 6, i32 7> -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I5_I]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> -// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]]) -// CHECK-NEXT: ret <4 x i32> [[VMULL2_I_I]] -// -uint32x4_t test_vmull_high_u16(uint16x8_t a, uint16x8_t b) { - return vmull_high_u16(a, b); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vmull_high_u32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHUFFLE_I5_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> <i32 2, i32 3> -// CHECK-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[B]], <2 x i32> <i32 2, i32 3> -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I5_I]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> -// CHECK-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]]) -// CHECK-NEXT: ret <2 x i64> [[VMULL2_I_I]] -// -uint64x2_t test_vmull_high_u32(uint32x4_t a, uint32x4_t b) { - return vmull_high_u32(a, b); -} - // CHECK-LABEL: define dso_local <8 x i16> @test_vmlal_s8( // CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]], <8 x i8> noundef [[C:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -11806,28 +11642,6 @@ int64x2_t test_vqdmlsl_high_s32(int64x2_t a, int32x4_t b, int32x4_t c) { return vqdmlsl_high_s32(a, b, c); } -// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_p8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]]) -// CHECK-NEXT: ret <8 x i16> [[VMULL_I]] -// -poly16x8_t test_vmull_p8(poly8x8_t a, poly8x8_t b) { - return vmull_p8(a, b); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vmull_high_p8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHUFFLE_I5:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -// CHECK-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> -// CHECK-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[SHUFFLE_I5]], <8 x i8> [[SHUFFLE_I]]) -// CHECK-NEXT: ret <8 x i16> [[VMULL_I_I]] -// -poly16x8_t test_vmull_high_p8(poly8x16_t a, poly8x16_t b) { - return vmull_high_p8(a, b); -} - // CHECK-LABEL: define dso_local i64 @test_vaddd_s64( // CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index bf8e62feda8da..9e38a11380fc3 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -982,3 +982,220 @@ int64_t test_vshld_u64(int64_t a,int64_t b) { return (int64_t)vshld_u64(a, b); } +//===------------------------------------------------------===// +// 2.1.1.2.8. Widening Multiplication +//===------------------------------------------------------===// + +// LLVM-LABEL: @test_vmull_s8( +// CIR-LABEL: @vmull_s8( +int16x8_t test_vmull_s8(int8x8_t a, int8x8_t b) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.smull" %{{.*}}, %{{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s16i> + +// LLVM-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]]) +// LLVM-NEXT: ret <8 x i16> [[VMULL_I]] + return vmull_s8(a, b); +} + +// LLVM-LABEL: @test_vmull_s16( +// CIR-LABEL: @vmull_s16( +int32x4_t test_vmull_s16(int16x4_t a, int16x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.smull" %{{.*}}, %{{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s32i> + +// LLVM-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> +// LLVM-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> +// LLVM-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) +// LLVM-NEXT: ret <4 x i32> [[VMULL2_I]] + return vmull_s16(a, b); +} + +// LLVM-LABEL: @test_vmull_s32( +// CIR-LABEL: @vmull_s32( +int64x2_t test_vmull_s32(int32x2_t a, int32x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.smull" %{{.*}}, %{{.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>) -> !cir.vector<2 x !s64i> + +// LLVM-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> +// LLVM-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> +// LLVM-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) +// LLVM-NEXT: ret <2 x i64> [[VMULL2_I]] + return vmull_s32(a, b); +} + +// LLVM-LABEL: @test_vmull_u8( +// CIR-LABEL: @vmull_u8( +uint16x8_t test_vmull_u8(uint8x8_t a, uint8x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.umull" %{{.*}}, %{{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u16i> + +// LLVM-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]]) +// LLVM-NEXT: ret <8 x i16> [[VMULL_I]] + return vmull_u8(a, b); +} + +// LLVM-LABEL: @test_vmull_u16( +// CIR-LABEL: @vmull_u16( +uint32x4_t test_vmull_u16(uint16x4_t a, uint16x4_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.umull" %{{.*}}, %{{.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u32i> + +// LLVM-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> +// LLVM-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> +// LLVM-NEXT: [[VMULL2_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I]], <4 x i16> [[VMULL1_I]]) +// LLVM-NEXT: ret <4 x i32> [[VMULL2_I]] + return vmull_u16(a, b); +} + +// LLVM-LABEL: @test_vmull_u32( +// CIR-LABEL: @vmull_u32( +uint64x2_t test_vmull_u32(uint32x2_t a, uint32x2_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.umull" %{{.*}}, %{{.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>) -> !cir.vector<2 x !u64i> + +// LLVM-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> +// LLVM-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM-NEXT: [[VMULL1_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> +// LLVM-NEXT: [[VMULL2_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I]], <2 x i32> [[VMULL1_I]]) +// LLVM-NEXT: ret <2 x i64> [[VMULL2_I]] + return vmull_u32(a, b); +} + +// LLVM-LABEL: @test_vmull_high_s8( +// CIR-LABEL: @vmull_high_s8( +int16x8_t test_vmull_high_s8(int8x16_t a, int8x16_t b) { +// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_s8 +// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_s8 +// CIR: cir.call @vmull_s8([[HIGH_A]], [[HIGH_B]]) + +// LLVM-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +// LLVM-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[SHUFFLE_I5_I]], <8 x i8> [[SHUFFLE_I_I]]) +// LLVM-NEXT: ret <8 x i16> [[VMULL_I_I]] + return vmull_high_s8(a, b); +} + +// LLVM-LABEL: @test_vmull_high_s16( +// CIR-LABEL: @vmull_high_s16( +int32x4_t test_vmull_high_s16(int16x8_t a, int16x8_t b) { +// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_s16 +// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_s16 +// CIR: {{%.*}} = cir.call @vmull_s16([[HIGH_A]], [[HIGH_B]]) + +// LLVM-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7> +// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> [[B]], <4 x i32> <i32 4, i32 5, i32 6, i32 7> +// LLVM-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I5_I]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> +// LLVM-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> +// LLVM-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.smull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]]) +// LLVM-NEXT: ret <4 x i32> [[VMULL2_I_I]] + return vmull_high_s16(a, b); +} + +// LLVM-LABEL: @test_vmull_high_s32( +// CIR-LABEL: @vmull_high_s32( +int64x2_t test_vmull_high_s32(int32x4_t a, int32x4_t b) { +// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_s32 +// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_s32 +// CIR: {{%.*}} = cir.call @vmull_s32([[HIGH_A]], [[HIGH_B]]) + +// LLVM-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> <i32 2, i32 3> +// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[B]], <2 x i32> <i32 2, i32 3> +// LLVM-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I5_I]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> +// LLVM-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> +// LLVM-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.smull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]]) +// LLVM-NEXT: ret <2 x i64> [[VMULL2_I_I]] + return vmull_high_s32(a, b); +} + +// LLVM-LABEL: @test_vmull_high_u8( +// CIR-LABEL: @vmull_high_u8( +uint16x8_t test_vmull_high_u8(uint8x16_t a, uint8x16_t b) { +// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_u8 +// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_u8 +// CIR: {{%.*}} = cir.call @vmull_u8([[HIGH_A]], [[HIGH_B]]) + +// LLVM-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +// LLVM-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[SHUFFLE_I5_I]], <8 x i8> [[SHUFFLE_I_I]]) +// LLVM-NEXT: ret <8 x i16> [[VMULL_I_I]] + return vmull_high_u8(a, b); +} + +// LLVM-LABEL: @test_vmull_high_u16( +// CIR-LABEL: @vmull_high_u16( +uint32x4_t test_vmull_high_u16(uint16x8_t a, uint16x8_t b) { +// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_u16 +// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_u16 +// CIR: {{%.*}} = cir.call @vmull_u16([[HIGH_A]], [[HIGH_B]]) + +// LLVM-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7> +// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> [[B]], <4 x i32> <i32 4, i32 5, i32 6, i32 7> +// LLVM-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I5_I]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[SHUFFLE_I_I]] to <8 x i8> +// LLVM-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> +// LLVM-NEXT: [[VMULL2_I_I:%.*]] = call <4 x i32> @llvm.aarch64.neon.umull.v4i32(<4 x i16> [[VMULL_I_I]], <4 x i16> [[VMULL1_I_I]]) +// LLVM-NEXT: ret <4 x i32> [[VMULL2_I_I]] + return vmull_high_u16(a, b); +} + +// LLVM-LABEL: @test_vmull_high_u32( +// CIR-LABEL: @vmull_high_u32( +uint64x2_t test_vmull_high_u32(uint32x4_t a, uint32x4_t b) { +// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_u32 +// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_u32 +// CIR: {{%.*}} = cir.call @vmull_u32([[HIGH_A]], [[HIGH_B]]) + +// LLVM-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> <i32 2, i32 3> +// LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[B]], <2 x i32> <i32 2, i32 3> +// LLVM-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I5_I]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[SHUFFLE_I_I]] to <8 x i8> +// LLVM-NEXT: [[VMULL_I_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM-NEXT: [[VMULL1_I_I:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> +// LLVM-NEXT: [[VMULL2_I_I:%.*]] = call <2 x i64> @llvm.aarch64.neon.umull.v2i64(<2 x i32> [[VMULL_I_I]], <2 x i32> [[VMULL1_I_I]]) +// LLVM-NEXT: ret <2 x i64> [[VMULL2_I_I]] + return vmull_high_u32(a, b); +} + +// LLVM-LABEL: @test_vmull_p8( +// CIR-LABEL: @vmull_p8( +poly16x8_t test_vmull_p8(poly8x8_t a, poly8x8_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.pmull" %{{.*}}, %{{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s16i> + +// LLVM-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]]) +// LLVM-NEXT: ret <8 x i16> [[VMULL_I]] + return vmull_p8(a, b); +} + +// LLVM-LABEL: @test_vmull_high_p8( +// CIR-LABEL: @vmull_high_p8( +poly16x8_t test_vmull_high_p8(poly8x16_t a, poly8x16_t b) { +// CIR: [[HIGH_A:%.*]] = cir.call @vget_high_p8 +// CIR: [[HIGH_B:%.*]] = cir.call @vget_high_p8 +// CIR: {{%.*}} = cir.call @vmull_p8([[HIGH_A]], [[HIGH_B]]) + +// LLVM-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM: [[SHUFFLE_I5:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +// LLVM-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> +// LLVM-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[SHUFFLE_I5]], <8 x i8> [[SHUFFLE_I]]) +// LLVM-NEXT: ret <8 x i16> [[VMULL_I_I]] + return vmull_high_p8(a, b); +} >From 2b0200cefeaae3fe57da163424e7091e6c26a602 Mon Sep 17 00:00:00 2001 From: Pau Sum <[email protected]> Date: Wed, 25 Mar 2026 16:03:38 -0400 Subject: [PATCH 2/4] Remove checks for attributes --- clang/test/CodeGen/AArch64/neon/intrinsics.c | 28 ++++++++++---------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index 9e38a11380fc3..0f22a9c9aad01 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -991,7 +991,7 @@ int64_t test_vshld_u64(int64_t a,int64_t b) { int16x8_t test_vmull_s8(int8x8_t a, int8x8_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.smull" %{{.*}}, %{{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s16i> -// LLVM-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) // LLVM: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]]) // LLVM-NEXT: ret <8 x i16> [[VMULL_I]] return vmull_s8(a, b); @@ -1002,7 +1002,7 @@ int16x8_t test_vmull_s8(int8x8_t a, int8x8_t b) { int32x4_t test_vmull_s16(int16x4_t a, int16x4_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.smull" %{{.*}}, %{{.*}} : (!cir.vector<4 x !s16i>, !cir.vector<4 x !s16i>) -> !cir.vector<4 x !s32i> -// LLVM-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) // LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> // LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> // LLVM-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> @@ -1017,7 +1017,7 @@ int32x4_t test_vmull_s16(int16x4_t a, int16x4_t b) { int64x2_t test_vmull_s32(int32x2_t a, int32x2_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.smull" %{{.*}}, %{{.*}} : (!cir.vector<2 x !s32i>, !cir.vector<2 x !s32i>) -> !cir.vector<2 x !s64i> -// LLVM-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]]) // LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> // LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> // LLVM-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> @@ -1032,7 +1032,7 @@ int64x2_t test_vmull_s32(int32x2_t a, int32x2_t b) { uint16x8_t test_vmull_u8(uint8x8_t a, uint8x8_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.umull" %{{.*}}, %{{.*}} : (!cir.vector<8 x !u8i>, !cir.vector<8 x !u8i>) -> !cir.vector<8 x !u16i> -// LLVM-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) // LLVM: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]]) // LLVM-NEXT: ret <8 x i16> [[VMULL_I]] return vmull_u8(a, b); @@ -1043,7 +1043,7 @@ uint16x8_t test_vmull_u8(uint8x8_t a, uint8x8_t b) { uint32x4_t test_vmull_u16(uint16x4_t a, uint16x4_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.umull" %{{.*}}, %{{.*}} : (!cir.vector<4 x !u16i>, !cir.vector<4 x !u16i>) -> !cir.vector<4 x !u32i> -// LLVM-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) // LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> // LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> // LLVM-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> @@ -1058,7 +1058,7 @@ uint32x4_t test_vmull_u16(uint16x4_t a, uint16x4_t b) { uint64x2_t test_vmull_u32(uint32x2_t a, uint32x2_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.umull" %{{.*}}, %{{.*}} : (!cir.vector<2 x !u32i>, !cir.vector<2 x !u32i>) -> !cir.vector<2 x !u64i> -// LLVM-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <2 x i32> {{.*}} [[A:%.*]], <2 x i32> {{.*}} [[B:%.*]]) // LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> // LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> // LLVM-NEXT: [[VMULL_I:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> @@ -1075,7 +1075,7 @@ int16x8_t test_vmull_high_s8(int8x16_t a, int8x16_t b) { // CIR: [[HIGH_B:%.*]] = cir.call @vget_high_s8 // CIR: cir.call @vmull_s8([[HIGH_A]], [[HIGH_B]]) -// LLVM-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) // LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> // LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> // LLVM-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.smull.v8i16(<8 x i8> [[SHUFFLE_I5_I]], <8 x i8> [[SHUFFLE_I_I]]) @@ -1090,7 +1090,7 @@ int32x4_t test_vmull_high_s16(int16x8_t a, int16x8_t b) { // CIR: [[HIGH_B:%.*]] = cir.call @vget_high_s16 // CIR: {{%.*}} = cir.call @vmull_s16([[HIGH_A]], [[HIGH_B]]) -// LLVM-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) // LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7> // LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> [[B]], <4 x i32> <i32 4, i32 5, i32 6, i32 7> // LLVM-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I5_I]] to <8 x i8> @@ -1109,7 +1109,7 @@ int64x2_t test_vmull_high_s32(int32x4_t a, int32x4_t b) { // CIR: [[HIGH_B:%.*]] = cir.call @vget_high_s32 // CIR: {{%.*}} = cir.call @vmull_s32([[HIGH_A]], [[HIGH_B]]) -// LLVM-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]]) // LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> <i32 2, i32 3> // LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[B]], <2 x i32> <i32 2, i32 3> // LLVM-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I5_I]] to <8 x i8> @@ -1128,7 +1128,7 @@ uint16x8_t test_vmull_high_u8(uint8x16_t a, uint8x16_t b) { // CIR: [[HIGH_B:%.*]] = cir.call @vget_high_u8 // CIR: {{%.*}} = cir.call @vmull_u8([[HIGH_A]], [[HIGH_B]]) -// LLVM-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) // LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> // LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> // LLVM-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.umull.v8i16(<8 x i8> [[SHUFFLE_I5_I]], <8 x i8> [[SHUFFLE_I_I]]) @@ -1143,7 +1143,7 @@ uint32x4_t test_vmull_high_u16(uint16x8_t a, uint16x8_t b) { // CIR: [[HIGH_B:%.*]] = cir.call @vget_high_u16 // CIR: {{%.*}} = cir.call @vmull_u16([[HIGH_A]], [[HIGH_B]]) -// LLVM-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) // LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <8 x i16> [[A]], <8 x i16> [[A]], <4 x i32> <i32 4, i32 5, i32 6, i32 7> // LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <8 x i16> [[B]], <8 x i16> [[B]], <4 x i32> <i32 4, i32 5, i32 6, i32 7> // LLVM-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[SHUFFLE_I5_I]] to <8 x i8> @@ -1162,7 +1162,7 @@ uint64x2_t test_vmull_high_u32(uint32x4_t a, uint32x4_t b) { // CIR: [[HIGH_B:%.*]] = cir.call @vget_high_u32 // CIR: {{%.*}} = cir.call @vmull_u32([[HIGH_A]], [[HIGH_B]]) -// LLVM-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <4 x i32> {{.*}} [[A:%.*]], <4 x i32> {{.*}} [[B:%.*]]) // LLVM: [[SHUFFLE_I5_I:%.*]] = shufflevector <4 x i32> [[A]], <4 x i32> [[A]], <2 x i32> <i32 2, i32 3> // LLVM-NEXT: [[SHUFFLE_I_I:%.*]] = shufflevector <4 x i32> [[B]], <4 x i32> [[B]], <2 x i32> <i32 2, i32 3> // LLVM-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[SHUFFLE_I5_I]] to <8 x i8> @@ -1179,7 +1179,7 @@ uint64x2_t test_vmull_high_u32(uint32x4_t a, uint32x4_t b) { poly16x8_t test_vmull_p8(poly8x8_t a, poly8x8_t b) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.pmull" %{{.*}}, %{{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s16i> -// LLVM-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) // LLVM: [[VMULL_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[A]], <8 x i8> [[B]]) // LLVM-NEXT: ret <8 x i16> [[VMULL_I]] return vmull_p8(a, b); @@ -1192,7 +1192,7 @@ poly16x8_t test_vmull_high_p8(poly8x16_t a, poly8x16_t b) { // CIR: [[HIGH_B:%.*]] = cir.call @vget_high_p8 // CIR: {{%.*}} = cir.call @vmull_p8([[HIGH_A]], [[HIGH_B]]) -// LLVM-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { +// LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) // LLVM: [[SHUFFLE_I5:%.*]] = shufflevector <16 x i8> [[A]], <16 x i8> [[A]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> // LLVM-NEXT: [[SHUFFLE_I:%.*]] = shufflevector <16 x i8> [[B]], <16 x i8> [[B]], <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> // LLVM-NEXT: [[VMULL_I_I:%.*]] = call <8 x i16> @llvm.aarch64.neon.pmull.v8i16(<8 x i8> [[SHUFFLE_I5]], <8 x i8> [[SHUFFLE_I]]) >From 346888836661bd65354a5554a873d0967f2c8713 Mon Sep 17 00:00:00 2001 From: Pau Sum <[email protected]> Date: Wed, 25 Mar 2026 16:22:01 -0400 Subject: [PATCH 3/4] Upstream helper 'getExtendedOrTruncatedElementVectorType' --- clang/lib/CIR/CodeGen/CIRGenBuilder.h | 37 +++++++++++++++++++ .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 8 +--- 2 files changed, 39 insertions(+), 6 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuilder.h b/clang/lib/CIR/CodeGen/CIRGenBuilder.h index 6cf27126e3bc6..fb047919b003d 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuilder.h +++ b/clang/lib/CIR/CodeGen/CIRGenBuilder.h @@ -397,6 +397,43 @@ class CIRGenBuilderTy : public cir::CIRBaseBuilderTy { } bool isInt(mlir::Type i) { return mlir::isa<cir::IntType>(i); } + cir::IntType getExtendedIntTy(cir::IntType ty, bool isSigned) { + switch (ty.getWidth()) { + case 8: + return isSigned ? typeCache.sInt16Ty : typeCache.uInt16Ty; + case 16: + return isSigned ? typeCache.sInt32Ty : typeCache.uInt32Ty; + case 32: + return isSigned ? typeCache.sInt64Ty : typeCache.uInt64Ty; + default: + llvm_unreachable("NYI"); + } + } + + cir::IntType getTruncatedIntTy(cir::IntType ty, bool isSigned) { + switch (ty.getWidth()) { + case 16: + return isSigned ? typeCache.sInt8Ty : typeCache.uInt8Ty; + case 32: + return isSigned ? typeCache.sInt16Ty : typeCache.uInt16Ty; + case 64: + return isSigned ? typeCache.sInt32Ty : typeCache.uInt32Ty; + default: + llvm_unreachable("NYI"); + } + } + + cir::VectorType + getExtendedOrTruncatedElementVectorType(cir::VectorType vt, bool isExtended, + bool isSigned = false) { + auto elementTy = mlir::dyn_cast_or_null<cir::IntType>(vt.getElementType()); + assert(elementTy && "expected int vector"); + return cir::VectorType::get(isExtended + ? getExtendedIntTy(elementTy, isSigned) + : getTruncatedIntTy(elementTy, isSigned), + vt.getSize()); + } + // Fetch the type representing a pointer to unsigned int8 values. cir::PointerType getUInt8PtrTy() { return typeCache.uInt8PtrTy; } diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 955d6b677390d..83e2af4ffa828 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -2215,12 +2215,8 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, intrName = usgn ? "aarch64.neon.umull" : "aarch64.neon.smull"; if (type.isPoly()) intrName = "aarch64.neon.pmull"; - // Widening multiply: args have half the element width of the result. - auto resultIntTy = mlir::cast<cir::IntType>(ty.getElementType()); - auto narrowIntTy = - cir::IntType::get(builder.getContext(), resultIntTy.getWidth() / 2, - resultIntTy.isSigned()); - auto argTy = cir::VectorType::get(narrowIntTy, ty.getSize()); + cir::VectorType argTy = builder.getExtendedOrTruncatedElementVectorType( + ty, false /* truncated */, !usgn); return emitNeonCall(cgm, builder, {argTy, argTy}, ops, intrName, ty, loc); } case NEON::BI__builtin_neon_vmax_v: >From 340408a3018956d76b5761ed398c94bcda29c86a Mon Sep 17 00:00:00 2001 From: Pau Sum <[email protected]> Date: Wed, 25 Mar 2026 17:55:53 -0400 Subject: [PATCH 4/4] Add the rest of polynomial multiply --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 8 ++++++ clang/test/CodeGen/AArch64/neon-intrinsics.c | 20 -------------- clang/test/CodeGen/AArch64/neon/intrinsics.c | 26 +++++++++++++++++++ 3 files changed, 34 insertions(+), 20 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 83e2af4ffa828..523160c913712 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -450,6 +450,14 @@ static mlir::Value emitCommonNeonBuiltinExpr( case NEON::BI__builtin_neon_vfmlslq_high_f16: case NEON::BI__builtin_neon_vmmlaq_s32: case NEON::BI__builtin_neon_vmmlaq_u32: + cgf.cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AArch64 builtin call: ") + + ctx.BuiltinInfo.getName(builtinID)); + return mlir::Value{}; + case NEON::BI__builtin_neon_vmul_v: + case NEON::BI__builtin_neon_vmulq_v: + return cgf.getBuilder().emitIntrinsicCallOp(loc, "aarch64.neon.pmul", vTy, + ops); case NEON::BI__builtin_neon_vusmmlaq_s32: case NEON::BI__builtin_neon_vusdot_s32: case NEON::BI__builtin_neon_vusdotq_s32: diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index 570343a538ce2..308375fd8b42d 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -539,26 +539,6 @@ float64x2_t test_vmulq_f64(float64x2_t v1, float64x2_t v2) { return vmulq_f64(v1, v2); } -// CHECK-LABEL: define dso_local <8 x i8> @test_vmul_p8( -// CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VMUL_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.pmul.v8i8(<8 x i8> [[V1]], <8 x i8> [[V2]]) -// CHECK-NEXT: ret <8 x i8> [[VMUL_V_I]] -// -poly8x8_t test_vmul_p8(poly8x8_t v1, poly8x8_t v2) { - return vmul_p8(v1, v2); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vmulq_p8( -// CHECK-SAME: <16 x i8> noundef [[V1:%.*]], <16 x i8> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VMULQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.pmul.v16i8(<16 x i8> [[V1]], <16 x i8> [[V2]]) -// CHECK-NEXT: ret <16 x i8> [[VMULQ_V_I]] -// -poly8x16_t test_vmulq_p8(poly8x16_t v1, poly8x16_t v2) { - return vmulq_p8(v1, v2); -} - // CHECK-LABEL: define dso_local <8 x i8> @test_vmla_s8( // CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]], <8 x i8> noundef [[V3:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index 0f22a9c9aad01..ce2bb5e8c7b53 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -1174,6 +1174,32 @@ uint64x2_t test_vmull_high_u32(uint32x4_t a, uint32x4_t b) { return vmull_high_u32(a, b); } +//===------------------------------------------------------===// +// 2.1.1.3.1. Polynomial Multiply +//===------------------------------------------------------===// + +// LLVM-LABEL: @test_vmul_p8( +// CIR-LABEL: @vmul_p8( +poly8x8_t test_vmul_p8(poly8x8_t v1, poly8x8_t v2) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.pmul" %{{.*}}, %{{.*}} : (!cir.vector<8 x !s8i>, !cir.vector<8 x !s8i>) -> !cir.vector<8 x !s8i> + +// LLVM-SAME: <8 x i8> {{.*}} [[V1:%.*]], <8 x i8> {{.*}} [[V2:%.*]]) +// LLVM: [[VMUL_V_I:%.*]] = call <8 x i8> @llvm.aarch64.neon.pmul.v8i8(<8 x i8> [[V1]], <8 x i8> [[V2]]) +// LLVM-NEXT: ret <8 x i8> [[VMUL_V_I]] + return vmul_p8(v1, v2); +} + +// LLVM-LABEL: @test_vmulq_p8( +// CIR-LABEL: @vmulq_p8( +poly8x16_t test_vmulq_p8(poly8x16_t v1, poly8x16_t v2) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.pmul" %{{.*}}, %{{.*}} : (!cir.vector<16 x !s8i>, !cir.vector<16 x !s8i>) -> !cir.vector<16 x !s8i> + +// LLVM-SAME: <16 x i8> {{.*}} [[V1:%.*]], <16 x i8> {{.*}} [[V2:%.*]]) +// LLVM: [[VMULQ_V_I:%.*]] = call <16 x i8> @llvm.aarch64.neon.pmul.v16i8(<16 x i8> [[V1]], <16 x i8> [[V2]]) +// LLVM-NEXT: ret <16 x i8> [[VMULQ_V_I]] + return vmulq_p8(v1, v2); +} + // LLVM-LABEL: @test_vmull_p8( // CIR-LABEL: @vmull_p8( poly16x8_t test_vmull_p8(poly8x8_t a, poly8x8_t b) { _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
