================
@@ -1940,6 +1940,59 @@ let TargetPrefix = "riscv" in {
defm vwabdau : RISCVTernaryWide;
} // TargetPrefix = "riscv"
+// Zvzip - Reordering Structured Data in Vector Registers
+//===----------------------------------------------------------------------===//
+let TargetPrefix = "riscv" in {
+ multiclass RISCVZip {
+ // Input: (passthru, vector_in, vector_in, vl)
+ def "int_riscv_" # NAME :
+ DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>, llvm_anyvector_ty,
+ LLVMMatchType<1>, llvm_anyint_ty],
+ [IntrNoMem]>, RISCVVIntrinsic {
+ let VLOperand = 3;
+ }
+
+ // Input: (maskedoff, vector_in, vector_in, mask, vl, policy)
+ def "int_riscv_" # NAME # "_mask" :
+ DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>, llvm_anyvector_ty,
+ LLVMMatchType<1>,
+ LLVMScalarOrSameVectorWidth<1, llvm_i1_ty>,
+ llvm_anyint_ty, LLVMMatchType<2>],
+ [ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic
{
+ let VLOperand = 4;
+ }
+ }
+
+ multiclass RISCVUnzip {
+ // Input: (passthru, vector_in, vl)
+ def "int_riscv_" # NAME :
+ DefaultAttrsIntrinsic<[llvm_anyvector_ty],
+ [LLVMMatchType<0>, llvm_anyvector_ty,
----------------
lukel97 wrote:
The @llvm.vector.interleave intrinsics use `LLVMOneNthElementsVectorType<0, 2>`
to specify the input vectors need to be exactly half the number of elements as
the output vectors, can we use them here too?
https://github.com/llvm/llvm-project/pull/186342
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