================
@@ -1729,6 +1729,27 @@ void PPCAsmPrinter::emitInstruction(const MachineInstr
*MI) {
EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::EnforceIEIO));
return;
}
+ case PPC::BL8:
+ case PPC::BL8_NOP: {
+ const MachineOperand &MO = MI->getOperand(0);
+ if (MO.isSymbol()) {
+ StringRef Name = MO.getSymbolName();
+ Name.consume_front(".");
+ Name.consume_back("[PR]");
+ bool IsLWAT = Name == "__lwat_csne_pseudo";
+ bool IsLDAT = Name == "__ldat_csne_pseudo";
+ if (IsLWAT || IsLDAT) {
----------------
maryammo wrote:
Custom inserter pseudo with implicit defs/uses fails for LWAT CSNE. The
instruction requires X3 (output-only), X4/X5 (inputs preloaded with compare/new
values), and address in a different register. Despite declaring
Uses=[X3,X4,X5], Defs=[X3], register allocator still assigns X3 to the address
operand, producing invalid assembly lwat 3,3,16. It seems no constraint
prevents this register conflict.
This is the pesudo and new code-gen only definitions I tried :
```
+let Uses = [X3, X4, X5], Defs = [X3], hasExtraSrcRegAllocReq = 1,
+ mayLoad = 1, mayStore = 1,
+ isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in
+def LWAT_CSNE : X_RD5_RS5_IM5<31, 582, (outs), (ins ptr_rc_nor0:$RA,
u5imm:$RB),
+ "lwat 3, $RA, $RB", IIC_LdStLoad>,
+ Requires<[IsISA3_0]> {
+ let RST = X3.HWEncoding{4-0};
+}
+
+let Defs = [R3, R4, R5] in
+def LWAT_CSNE_PSEUDO : PPCCustomInserterPseudo<
+ (outs gprc:$dst),
+ (ins ptr_rc_nor0:$ptr, gprc:$cmp_val, gprc:$new_val),
+ "#LWAT_CSNE_PSEUDO",
+ [(set i32:$dst, (int_ppc_amo_lwat_csne ptr_rc_nor0:$ptr, gprc:$cmp_val,
gprc:$new_val))]>;
+
```
https://github.com/llvm/llvm-project/pull/178061
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