https://github.com/resistor updated https://github.com/llvm/llvm-project/pull/189968
>From 0a88483062aab7028d804a6770b43eb78916ca26 Mon Sep 17 00:00:00 2001 From: Owen Anderson <[email protected]> Date: Wed, 1 Apr 2026 16:15:08 +0200 Subject: [PATCH 1/2] [CHERIoT] Define a RISCV target feature for XCheriot. The specification for this extension is publically available here: https://github.com/CHERIoT-Platform/cheriot-sail/releases/download/v1.0/cheriot-architecture-v1.0.pdf This change only adds the target feature, without adding any functionality gated by it yet. This change is intended to enable DataLayout-related changes in TargetParser, which depend on RISCVISAInfo being able at least to recognize the name of this extension. --- llvm/lib/Target/RISCV/RISCVFeatures.td | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 59525fb0a469e..a166524ad15ff 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1750,6 +1750,13 @@ def HasXAIFET : Predicate<"Subtarget->hasXAIFET()">, AssemblerPredicate<(all_of FeatureVendorXAIFET), "'XAIFET' (AI Foundry ET Extension)">; +def FeatureVendorXCheriot + : RISCVExtension<1, 0, "CHERIoT extension", + [FeatureStdExtC, FeatureStdExtE, FeatureStdExtM]>; +def HasCheriot + : Predicate<"Subtarget->hasVendorXCheriot()">, + AssemblerPredicate<(all_of FeatureVendorXCheriot), "'XCheriot' (CHERIoT Extension)">; + //===----------------------------------------------------------------------===// // LLVM specific features and extensions //===----------------------------------------------------------------------===// >From 97f82d3ae8a1eecca176057d78eb9e92ce58167f Mon Sep 17 00:00:00 2001 From: Owen Anderson <[email protected]> Date: Wed, 1 Apr 2026 17:45:02 +0200 Subject: [PATCH 2/2] Update tests for new feature. --- clang/test/Driver/print-supported-extensions-riscv.c | 1 + llvm/test/CodeGen/RISCV/features-info.ll | 1 + llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 1 + 3 files changed, 3 insertions(+) diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c index b9696f0c7ec7d..1a832451ed7bc 100644 --- a/clang/test/Driver/print-supported-extensions-riscv.c +++ b/clang/test/Driver/print-supported-extensions-riscv.c @@ -170,6 +170,7 @@ // CHECK-NEXT: xandesvpackfph 5.0 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension) // CHECK-NEXT: xandesvsinth 5.0 'XAndesVSIntH' (Andes Vector Small INT Handling Extension) // CHECK-NEXT: xandesvsintload 5.0 'XAndesVSIntLoad' (Andes Vector INT4 Load Extension) +// CHECK-NEXT: xcheriot 1.0 'XCheriot' (CHERIoT extension) // CHECK-NEXT: xcvalu 1.0 'XCValu' (CORE-V ALU Operations) // CHECK-NEXT: xcvbi 1.0 'XCVbi' (CORE-V Immediate Branching) // CHECK-NEXT: xcvbitmanip 1.0 'XCVbitmanip' (CORE-V Bit Manipulation) diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll index 5a137a9dbbc3a..7c4271b409f82 100644 --- a/llvm/test/CodeGen/RISCV/features-info.ll +++ b/llvm/test/CodeGen/RISCV/features-info.ll @@ -195,6 +195,7 @@ ; CHECK-NEXT: xandesvpackfph - 'XAndesVPackFPH' (Andes Vector Packed FP16 Extension). ; CHECK-NEXT: xandesvsinth - 'XAndesVSIntH' (Andes Vector Small INT Handling Extension). ; CHECK-NEXT: xandesvsintload - 'XAndesVSIntLoad' (Andes Vector INT4 Load Extension). +; CHECK-NEXT: xcheriot - 'XCheriot' (CHERIoT extension). ; CHECK-NEXT: xcvalu - 'XCValu' (CORE-V ALU Operations). ; CHECK-NEXT: xcvbi - 'XCVbi' (CORE-V Immediate Branching). ; CHECK-NEXT: xcvbitmanip - 'XCVbitmanip' (CORE-V Bit Manipulation). diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 5c7b8c665a9b2..ca2c28c30a30f 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -1301,6 +1301,7 @@ R"(All available -march extensions for RISC-V xandesvpackfph 5.0 xandesvsinth 5.0 xandesvsintload 5.0 + xcheriot 1.0 xcvalu 1.0 xcvbi 1.0 xcvbitmanip 1.0 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
