================
@@ -3018,3 +3018,380 @@ mfloat8x16_t test_vbslq_mf8(uint8x16_t v1, mfloat8x16_t
v2, mfloat8x16_t v3) {
// LLVM: ret <16 x i8> [[VBSL2_I]]
return vbslq_mf8(v1, v2, v3);
}
+
+//===------------------------------------------------------===//
+// 2.1.3.2.4 Vector rounding shift right and accumulate
+//
https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-rounding-shift-right-and-accumulate
+//===------------------------------------------------------===//
+
+// LLVM-LABEL: @test_vrsra_n_s8(
+// CIR-LABEL: @test_vrsra_n_s8(
----------------
banach-space wrote:
```suggestion
// ALL-LABEL: @test_vrsra_n_s8(
```
Here and in other places.
https://github.com/llvm/llvm-project/pull/191129
_______________________________________________
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
