https://github.com/AmrDeveloper created https://github.com/llvm/llvm-project/pull/196836
Implement support for TernaryOp for Vec in OpenCL Issue https://github.com/llvm/llvm-project/issues/192311 >From 251b710e136f90a992b25169be03788494568b60 Mon Sep 17 00:00:00 2001 From: Amr Hesham <[email protected]> Date: Sun, 10 May 2026 21:44:55 +0200 Subject: [PATCH] [CIR] Implement TernaryOp for Vec in OpenCL --- clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp | 24 ++++++++++- clang/test/CIR/CodeGenOpenCL/vector.cl | 46 ++++++++++++++++++++++ 2 files changed, 69 insertions(+), 1 deletion(-) create mode 100644 clang/test/CIR/CodeGenOpenCL/vector.cl diff --git a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp index 231039ec5da29..afce85778b45d 100644 --- a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp @@ -2778,7 +2778,29 @@ mlir::Value ScalarExprEmitter::VisitAbstractConditionalOperator( if (cgf.getLangOpts().OpenCL && (condType->isVectorType() || condType->isExtVectorType())) { assert(!cir::MissingFeatures::vectorType()); - cgf.cgm.errorNYI(e->getSourceRange(), "OpenCL vector ternary op"); + + mlir::Value condValue = cgf.emitScalarExpr(condExpr); + mlir::Value lhsValue = Visit(lhsExpr); + mlir::Value rhsValue = Visit(rhsExpr); + + mlir::Type vecTy = convertType(condType); + mlir::Value zeroVec = builder.getNullValue(vecTy, loc); + auto testMSB = cir::VecCmpOp::create( + builder, loc, vecTy, cir::CmpOpKind::lt, condValue, zeroVec); + mlir::Value tmp = builder.createIntCast(testMSB, vecTy); + mlir::Value tmp2 = builder.createNot(testMSB); + + auto rhsVecTy = cast<cir::VectorType>(rhsValue.getType()); + // Cast float to int to perform ANDs if necessary. + if (rhsVecTy.getElementType().isFloat()) { + cgf.cgm.errorNYI(loc, "VisitAbstractConditionalOperator: OpenCL " + "TernaryOp Vec of type float"); + return {}; + } + + mlir::Value tmp3 = builder.createAnd(loc, rhsValue, tmp2); + mlir::Value tmp4 = builder.createAnd(loc, lhsValue, tmp); + return builder.createOr(loc, tmp3, tmp4); } if (condType->isVectorType() || condType->isSveVLSBuiltinType()) { diff --git a/clang/test/CIR/CodeGenOpenCL/vector.cl b/clang/test/CIR/CodeGenOpenCL/vector.cl new file mode 100644 index 0000000000000..ede32697ce2a1 --- /dev/null +++ b/clang/test/CIR/CodeGenOpenCL/vector.cl @@ -0,0 +1,46 @@ +// RUN: %clang_cc1 %s -fclangir -emit-cir -triple spir-unknown-unknown -o %t.cir +// RUN: FileCheck %s --input-file=%t.cir --check-prefix=CIR + +// RUN: %clang_cc1 %s -fclangir -emit-llvm -triple spir-unknown-unknown -o %t.ll +// RUN: FileCheck %s --input-file=%t.ll --check-prefix=LLVM + +// RUN: %clang_cc1 %s -emit-llvm -triple spir-unknown-unknown -o %t.ll +// RUN: FileCheck %s --input-file=%t.ll --check-prefix=OGCG + +typedef __attribute__(( ext_vector_type(4) )) int int4; + +int4 vec_ternary(int4 c, int4 a, int4 b) { + return c ? a : c; +} + +// CIR: %[[C_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["c", init] +// CIR: %[[A_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["a", init] +// CIR: %[[B_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["b", init] +// CIR: %[[RET_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["__retval"] +// CIR: cir.store %{{.*}}, %[[C_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>> +// CIR: cir.store %{{.*}}, %[[A_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>> +// CIR: cir.store %{{.*}}, %[[B_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>> +// CIR: %[[TMP_C:.*]] = cir.load {{.*}} %[[C_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_A:.*]] = cir.load {{.*}} %[[A_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i> +// CIR: %[[TMP_C_2:.*]] = cir.load {{.*}} %[[C_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i> +// CIR: %[[CONST_0_VEC:.*]] = cir.const #cir.zero : !cir.vector<4 x !s32i> +// CIR: %[[C_CMP:.*]] = cir.vec.cmp(lt, %[[TMP_C]], %[[CONST_0_VEC]]) : !cir.vector<4 x !s32i>, !cir.vector<4 x !s32i> +// CIR: %[[C_CMP_NOT:.*]] = cir.not %[[C_CMP]] : !cir.vector<4 x !s32i> +// CIR: %[[TMP_2:.*]] = cir.and %[[TMP_C_2]], %[[C_CMP_NOT]] : !cir.vector<4 x !s32i> +// CIR: %[[TMP_3:.*]] = cir.and %[[TMP_A]], %[[C_CMP]] : !cir.vector<4 x !s32i> +// CIR: %[[RESULT:.*]] = cir.or %[[TMP_2]], %[[TMP_3]] : !cir.vector<4 x !s32i> +// CIR: cir.store %[[RESULT]], %[[RET_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>> +// CIR: %[[RET_VAL:.*]] = cir.load %[[RET_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i> +// CIR: cir.return %[[RET_VAL]] : !cir.vector<4 x !s32i> + +// LLVM: %[[COND_MAX:.*]] = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> %[[COND:.*]], <4 x i32> zeroinitializer) +// LLVM: %[[COND_IS_NEG:.*]] = icmp slt <4 x i32> %[[COND]], zeroinitializer +// LLVM: %[[SELECT:.*]] = select <4 x i1> %[[COND_IS_NEG]], <4 x i32> %[[A:.*]], <4 x i32> zeroinitializer +// LLVM: %[[RESULT:.*]] = or <4 x i32> %[[SELECT]], %[[COND_MAX]] +// LLVM: ret <4 x i32> %[[RESULT]] + +// OGCG: %[[COND_MAX:.*]] = tail call <4 x i32> @llvm.smax.v4i32(<4 x i32> %[[COND:.*]], <4 x i32> zeroinitializer) +// OGCG: %[[COND_IS_NEG:.*]] = icmp slt <4 x i32> %[[COND]], zeroinitializer +// OGCG: %[[SELECT:.*]] = select <4 x i1> %[[COND_IS_NEG]], <4 x i32> %[[A:.*]], <4 x i32> zeroinitializer +// OGCG: %[[RESULT:.*]] = or <4 x i32> %[[SELECT]], %[[COND_MAX]] +// OGCG: ret <4 x i32> %[[RESULT]] _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
