github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
<details>
<summary>
You can test this locally with the following command:
</summary>
``````````bash
git-clang-format --diff origin/main HEAD --extensions c,h,cpp --
clang/test/CodeGen/PowerPC/half-float16-ppc.c clang/lib/Basic/Targets/PPC.cpp
clang/lib/Basic/Targets/PPC.h clang/lib/Driver/ToolChains/Arch/PPC.cpp
llvm/lib/Target/PowerPC/GISel/PPCRegisterBankInfo.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.h --diff_from_common_commit
``````````
:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:
</details>
<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index cc843df59..50a97985a 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -7057,9 +7057,10 @@ static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
}
// So far, this function is only used by LowerFormalArguments_AIX()
-static const TargetRegisterClass *
-getRegClassForSVT(MVT::SimpleValueType SVT, bool IsPPC64, bool HasP8Vector,
- bool HasVSX) {
+static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT,
+ bool IsPPC64,
+ bool HasP8Vector,
+ bool HasVSX) {
assert((IsPPC64 || SVT != MVT::i64) &&
"i64 should have been split for 32-bit codegen.");
@@ -7218,9 +7219,8 @@ SDValue PPCTargetLowering::LowerFormalArguments_AIX(
continue;
if (SaveParams && VA.isRegLoc() && !Flags.isByVal() && !VA.needsCustom()) {
- const TargetRegisterClass *RegClass =
- getRegClassForSVT(LocVT.SimpleTy, IsPPC64, Subtarget.hasP8Vector(),
- Subtarget.hasVSX());
+ const TargetRegisterClass *RegClass = getRegClassForSVT(
+ LocVT.SimpleTy, IsPPC64, Subtarget.hasP8Vector(),
Subtarget.hasVSX());
// On PPC64, debugger assumes extended 8-byte values are stored from GPR.
MVT SaveVT = RegClass == &PPC::G8RCRegClass ? MVT::i64 : LocVT;
const Register VReg = MF.addLiveIn(VA.getLocReg(), RegClass);
@@ -7445,10 +7445,10 @@ SDValue PPCTargetLowering::LowerFormalArguments_AIX(
if (VA.isRegLoc() && !VA.needsCustom()) {
MVT::SimpleValueType SVT = ValVT.SimpleTy;
- Register VReg = MF.addLiveIn(
- VA.getLocReg(),
- getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(),
- Subtarget.hasVSX()));
+ Register VReg =
+ MF.addLiveIn(VA.getLocReg(),
+ getRegClassForSVT(SVT, IsPPC64, Subtarget.hasP8Vector(),
+ Subtarget.hasVSX()));
SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
if (ValVT.isScalarInteger() &&
(ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits())) {
``````````
</details>
https://github.com/llvm/llvm-project/pull/196559
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