https://github.com/Siya-05 updated https://github.com/llvm/llvm-project/pull/196079
>From 00f545475131364aba04009d94f95cdcbc329098 Mon Sep 17 00:00:00 2001 From: Sivapriya Venkateswarar <[email protected]> Date: Wed, 6 May 2026 17:36:31 +0400 Subject: [PATCH 1/5] [CIR][CUDA] Support built-in CUDA surface type --- clang/lib/CIR/CodeGen/CIRGenTypes.cpp | 8 ++++++++ clang/lib/CIR/CodeGen/TargetInfo.cpp | 6 ++++++ clang/lib/CIR/CodeGen/TargetInfo.h | 4 ++++ clang/test/CIR/CodeGenCUDA/surface.cu | 21 +++++++++++++++++++++ 4 files changed, 39 insertions(+) create mode 100644 clang/test/CIR/CodeGenCUDA/surface.cu diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp index 85b7e854abb7f..308e1b44a6352 100644 --- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp @@ -295,6 +295,14 @@ mlir::Type CIRGenTypes::convertType(QualType type) { type = astContext.getCanonicalType(type); const Type *ty = type.getTypePtr(); + if (astContext.getLangOpts().CUDAIsDevice) { + if (type->isCUDADeviceBuiltinSurfaceType()) { + if (mlir::Type ty = + cgm.getTargetCIRGenInfo().getCUDADeviceBuiltinSurfaceDeviceType()) + return ty; + } + } + // Process record types before the type cache lookup. if (const auto *recordType = dyn_cast<RecordType>(type)) return convertRecordDeclType(recordType->getDecl()->getDefinitionOrSelf()); diff --git a/clang/lib/CIR/CodeGen/TargetInfo.cpp b/clang/lib/CIR/CodeGen/TargetInfo.cpp index f674299168960..658e46a2a9e4f 100644 --- a/clang/lib/CIR/CodeGen/TargetInfo.cpp +++ b/clang/lib/CIR/CodeGen/TargetInfo.cpp @@ -130,6 +130,12 @@ class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo { public: NVPTXTargetCIRGenInfo(CIRGenTypes &cgt) : TargetCIRGenInfo(std::make_unique<NVPTXABIInfo>(cgt)) {} + + mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override { + // CUDA surface is represented as a 64-bit handle on device + return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64, + /*isSigned=*/true); + } }; } // namespace diff --git a/clang/lib/CIR/CodeGen/TargetInfo.h b/clang/lib/CIR/CodeGen/TargetInfo.h index 5e0103093827b..f64305df5bccf 100644 --- a/clang/lib/CIR/CodeGen/TargetInfo.h +++ b/clang/lib/CIR/CodeGen/TargetInfo.h @@ -63,6 +63,10 @@ class TargetCIRGenInfo { cir::LangAddressSpace::Default); } + virtual mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const { + return nullptr; + } + /// Determine whether a call to an unprototyped functions under /// the given calling convention should use the variadic /// convention or the non-variadic convention. diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu b/clang/test/CIR/CodeGenCUDA/surface.cu new file mode 100644 index 0000000000000..d28f876080180 --- /dev/null +++ b/clang/test/CIR/CodeGenCUDA/surface.cu @@ -0,0 +1,21 @@ +// REQUIRES: x86-registered-target +// REQUIRES: nvptx-registered-target +// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s +// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-LLVM %s + +struct surfaceReference { + int desc; +}; + +template <typename T, int dim = 1> +struct __attribute__((device_builtin_surface_type)) surface + : public surfaceReference {}; + +template <int dim> +struct __attribute__((device_builtin_surface_type)) surface<void, dim> + : public surfaceReference {}; + +surface<void, 2> surf; + +// DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison : !s64i +// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64 poison \ No newline at end of file >From 0f88956e014d319c981effdf1fc7e7d9a6edef1c Mon Sep 17 00:00:00 2001 From: Sivapriya Venkateswarar <[email protected]> Date: Fri, 8 May 2026 14:12:08 +0400 Subject: [PATCH 2/5] [CIR][CUDA] Add trailing newline to surface test --- clang/test/CIR/CodeGenCUDA/surface.cu | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu b/clang/test/CIR/CodeGenCUDA/surface.cu index d28f876080180..6044d63f85dd3 100644 --- a/clang/test/CIR/CodeGenCUDA/surface.cu +++ b/clang/test/CIR/CodeGenCUDA/surface.cu @@ -18,4 +18,4 @@ struct __attribute__((device_builtin_surface_type)) surface<void, dim> surface<void, 2> surf; // DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison : !s64i -// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64 poison \ No newline at end of file +// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64 poison >From 628756a8f56cd27f93c8b4dccfeb02ce6271a60b Mon Sep 17 00:00:00 2001 From: Sivapriya Venkateswarar <[email protected]> Date: Mon, 18 May 2026 07:55:35 +0400 Subject: [PATCH 3/5] [CIR][CUDA] Mark texture type as missing --- clang/include/clang/CIR/MissingFeatures.h | 1 + clang/lib/CIR/CodeGen/CIRGenTypes.cpp | 3 +++ 2 files changed, 4 insertions(+) diff --git a/clang/include/clang/CIR/MissingFeatures.h b/clang/include/clang/CIR/MissingFeatures.h index eea858e3aa8cb..a6bbd845ee2f7 100644 --- a/clang/include/clang/CIR/MissingFeatures.h +++ b/clang/include/clang/CIR/MissingFeatures.h @@ -242,6 +242,7 @@ struct MissingFeatures { static bool ctorConstLvalueToRvalueConversion() { return false; } static bool ctorMemcpyizer() { return false; } static bool cudaSupport() { return false; } + static bool cudaTextureType() { return false; } static bool hipModuleCtor() { return false; } static bool globalRegistration() { return false; } static bool dataLayoutTypeIsSized() { return false; } diff --git a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp index 308e1b44a6352..d0cd751cd5d47 100644 --- a/clang/lib/CIR/CodeGen/CIRGenTypes.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenTypes.cpp @@ -10,6 +10,7 @@ #include "clang/AST/Type.h" #include "clang/Basic/TargetInfo.h" #include "clang/CIR/Dialect/IR/CIRTypes.h" +#include "clang/CIR/MissingFeatures.h" #include <cassert> @@ -300,6 +301,8 @@ mlir::Type CIRGenTypes::convertType(QualType type) { if (mlir::Type ty = cgm.getTargetCIRGenInfo().getCUDADeviceBuiltinSurfaceDeviceType()) return ty; + } else if (type->isCUDADeviceBuiltinTextureType()) { + assert(!cir::MissingFeatures::cudaTextureType()); } } >From 5a976ae569ae6d2e8f33454c6d1b61bb0a00020d Mon Sep 17 00:00:00 2001 From: Sivapriya Venkateswarar <[email protected]> Date: Thu, 21 May 2026 20:09:01 +0400 Subject: [PATCH 4/5] [CIR][CUDA] Add OG CodeGen comparison for surface test --- clang/test/CIR/CodeGenCUDA/surface.cu | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu b/clang/test/CIR/CodeGenCUDA/surface.cu index 6044d63f85dd3..a03962ed5f263 100644 --- a/clang/test/CIR/CodeGenCUDA/surface.cu +++ b/clang/test/CIR/CodeGenCUDA/surface.cu @@ -1,7 +1,8 @@ // REQUIRES: x86-registered-target // REQUIRES: nvptx-registered-target // RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=DEVICE-CIR %s -// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-LLVM %s +// RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-CIR-LLVM %s +// RUN: %clang_cc1 -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=DEVICE-OGCG %s struct surfaceReference { int desc; @@ -18,4 +19,7 @@ struct __attribute__((device_builtin_surface_type)) surface<void, dim> surface<void, 2> surf; // DEVICE-CIR: cir.global external target_address_space(1) @surf = #cir.poison : !s64i -// DEVICE-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64 poison + +// CIR lowers poison to LLVM poison, while OG CodeGen emits undef. +// DEVICE-CIR-LLVM: @surf ={{.*}} addrspace(1) externally_initialized global i64 poison +// DEVICE-OGCG: @surf ={{.*}} addrspace(1) externally_initialized global i64 undef \ No newline at end of file >From 567e84c53e955c6526d7032084a3ca89fc3be94a Mon Sep 17 00:00:00 2001 From: Sivapriya Venkateswarar <[email protected]> Date: Sat, 23 May 2026 12:06:00 +0400 Subject: [PATCH 5/5] [CIR][NVPTX] Move target info to Targets directory --- clang/lib/CIR/CodeGen/CMakeLists.txt | 1 + clang/lib/CIR/CodeGen/TargetInfo.cpp | 25 -------------- clang/lib/CIR/CodeGen/Targets/NVPTX.cpp | 46 +++++++++++++++++++++++++ 3 files changed, 47 insertions(+), 25 deletions(-) create mode 100644 clang/lib/CIR/CodeGen/Targets/NVPTX.cpp diff --git a/clang/lib/CIR/CodeGen/CMakeLists.txt b/clang/lib/CIR/CodeGen/CMakeLists.txt index b59addbfd6beb..e9fed57c87cbc 100644 --- a/clang/lib/CIR/CodeGen/CMakeLists.txt +++ b/clang/lib/CIR/CodeGen/CMakeLists.txt @@ -54,6 +54,7 @@ add_clang_library(clangCIR CIRGenVTables.cpp TargetInfo.cpp Targets/AMDGPU.cpp + Targets/NVPTX.cpp DEPENDS MLIRCIR diff --git a/clang/lib/CIR/CodeGen/TargetInfo.cpp b/clang/lib/CIR/CodeGen/TargetInfo.cpp index 658e46a2a9e4f..7076f02000e15 100644 --- a/clang/lib/CIR/CodeGen/TargetInfo.cpp +++ b/clang/lib/CIR/CodeGen/TargetInfo.cpp @@ -119,36 +119,11 @@ class X8664TargetCIRGenInfo : public TargetCIRGenInfo { }; } // namespace -namespace { - -class NVPTXABIInfo : public ABIInfo { -public: - NVPTXABIInfo(CIRGenTypes &cgt) : ABIInfo(cgt) {} -}; - -class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo { -public: - NVPTXTargetCIRGenInfo(CIRGenTypes &cgt) - : TargetCIRGenInfo(std::make_unique<NVPTXABIInfo>(cgt)) {} - - mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override { - // CUDA surface is represented as a 64-bit handle on device - return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64, - /*isSigned=*/true); - } -}; -} // namespace - std::unique_ptr<TargetCIRGenInfo> clang::CIRGen::createAMDGPUTargetCIRGenInfo(CIRGenTypes &cgt) { return std::make_unique<AMDGPUTargetCIRGenInfo>(cgt); } -std::unique_ptr<TargetCIRGenInfo> -clang::CIRGen::createNVPTXTargetCIRGenInfo(CIRGenTypes &cgt) { - return std::make_unique<NVPTXTargetCIRGenInfo>(cgt); -} - std::unique_ptr<TargetCIRGenInfo> clang::CIRGen::createX8664TargetCIRGenInfo(CIRGenTypes &cgt) { return std::make_unique<X8664TargetCIRGenInfo>(cgt); diff --git a/clang/lib/CIR/CodeGen/Targets/NVPTX.cpp b/clang/lib/CIR/CodeGen/Targets/NVPTX.cpp new file mode 100644 index 0000000000000..a50f397da8e73 --- /dev/null +++ b/clang/lib/CIR/CodeGen/Targets/NVPTX.cpp @@ -0,0 +1,46 @@ +//===---- NVPTX.cpp - NVPTX-specific CIR CodeGen --------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This provides NVPTX-specific CIR CodeGen logic. +// +//===----------------------------------------------------------------------===// + +#include "../ABIInfo.h" +#include "../TargetInfo.h" + +#include "clang/CIR/Dialect/IR/CIRTypes.h" + +using namespace clang; +using namespace clang::CIRGen; + +namespace { + +class NVPTXABIInfo : public ABIInfo { +public: + NVPTXABIInfo(CIRGenTypes &cgt) : ABIInfo(cgt) {} +}; + +class NVPTXTargetCIRGenInfo : public TargetCIRGenInfo { +public: + NVPTXTargetCIRGenInfo(CIRGenTypes &cgt) + : TargetCIRGenInfo(std::make_unique<NVPTXABIInfo>(cgt)) {} + + mlir::Type getCUDADeviceBuiltinSurfaceDeviceType() const override { + // On the device side, surface reference is represented as an object handle + // in 64-bit integer. + return cir::IntType::get(&getABIInfo().cgt.getMLIRContext(), 64, + /*isSigned=*/true); + } +}; + +} // namespace + +std::unique_ptr<TargetCIRGenInfo> +clang::CIRGen::createNVPTXTargetCIRGenInfo(CIRGenTypes &cgt) { + return std::make_unique<NVPTXTargetCIRGenInfo>(cgt); +} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
