llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Jiahao Guo (E00N777) <details> <summary>Changes</summary> ### summary part of: https://github.com/llvm/llvm-project/issues/185382 this is a follow up of : https://github.com/llvm/llvm-project/pull/198309 This adds CIR lowering for the scalar AArch64 NEON shift-left-and-insert intrinsics `vslid_n_s64` and `vslid_n_u64`. These ACLE builtins expose scalar `i64` interfaces, but the corresponding LLVM intrinsic is vector-shaped: ```llvm llvm.aarch64.neon.vsli.v1i64(<1 x i64>, <1 x i64>, i32) -> <1 x i64> ``` The new lowering wraps the scalar 64-bit operands in one-lane CIR vector types, emits the aarch64.neon.vsli LLVM intrinsic call, and bitcasts the result back to the scalar return type. --- Full diff: https://github.com/llvm/llvm-project/pull/199415.diff 2 Files Affected: - (modified) clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp (+12) - (modified) clang/test/CodeGen/AArch64/neon/intrinsics.c (+31) ``````````diff diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 18ec9e24722bd..319333d8e46ff 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -357,6 +357,18 @@ static mlir::Value emitCommonNeonSISDBuiltinExpr( return emitNeonCall(cgf.cgm, cgf.getBuilder(), {cgf.convertType(expr->getArg(0)->getType())}, ops, llvmIntrName, cgf.convertType(expr->getType()), loc); + case NEON::BI__builtin_neon_vslid_n_s64: + case NEON::BI__builtin_neon_vslid_n_u64: { + // The LLVM intrinsic is aarch64.neon.vsli.v1i64, so wrap the i64 inputs + // in <1 x i64> and unwrap the result back to i64. + mlir::Type scalarTy = cgf.convertType(expr->getArg(0)->getType()); + cir::VectorType vecTy = cir::VectorType::get(scalarTy, 1); + llvm::SmallVector<mlir::Type> argTypes = {vecTy, vecTy, ops[2].getType()}; + mlir::Value result = emitNeonCall(cgf.cgm, cgf.getBuilder(), argTypes, ops, + llvmIntrName, vecTy, loc); + return cgf.getBuilder().createBitcast( + result, cgf.convertType(expr->getType())); + } } return nullptr; diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index b4fbdcc5436ed..07937d5209e45 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -5096,3 +5096,34 @@ uint64_t test_vaddlvq_u32(uint32x4_t a) { // LLVM-NEXT: ret i64 [[VADDLVQ_U32_I]] return vaddlvq_u32(a); } + +//===------------------------------------------------------===// +// 2.1.3.1.6. Vector shift left and insert (scalar) +// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-left-and-insert +//===------------------------------------------------------===// + +// ALL-LABEL: @test_vslid_n_s64( +int64_t test_vslid_n_s64(int64_t a, int64_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsli" %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<1 x !s64i>, !cir.vector<1 x !s64i>, !s32i) -> !cir.vector<1 x !s64i> + +// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast i64 [[A]] to <1 x i64> +// LLVM: [[TMP1:%.*]] = bitcast i64 [[B]] to <1 x i64> +// LLVM: [[VSLID:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64> [[TMP0]], <1 x i64> [[TMP1]], i32 63) +// LLVM: [[RET:%.*]] = bitcast <1 x i64> [[VSLID]] to i64 +// LLVM: ret i64 [[RET]] + return (int64_t)vslid_n_s64(a, b, 63); +} + +// ALL-LABEL: @test_vslid_n_u64( +uint64_t test_vslid_n_u64(uint64_t a, uint64_t b) { +// CIR: cir.call_llvm_intrinsic "aarch64.neon.vsli" %{{.*}}, %{{.*}}, %{{.*}} : (!cir.vector<1 x !u64i>, !cir.vector<1 x !u64i>, !s32i) -> !cir.vector<1 x !u64i> + +// LLVM-SAME: i64 {{.*}} [[A:%.*]], i64 {{.*}} [[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast i64 [[A]] to <1 x i64> +// LLVM: [[TMP1:%.*]] = bitcast i64 [[B]] to <1 x i64> +// LLVM: [[VSLID:%.*]] = call <1 x i64> @llvm.aarch64.neon.vsli.v1i64(<1 x i64> [[TMP0]], <1 x i64> [[TMP1]], i32 63) +// LLVM: [[RET:%.*]] = bitcast <1 x i64> [[VSLID]] to i64 +// LLVM: ret i64 [[RET]] + return (uint64_t)vslid_n_u64(a, b, 63); +} `````````` </details> https://github.com/llvm/llvm-project/pull/199415 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
