Author: Craig Topper Date: 2026-05-22T11:09:01-07:00 New Revision: 29b141740d263f11c8e1d8490522ed7674096faa
URL: https://github.com/llvm/llvm-project/commit/29b141740d263f11c8e1d8490522ed7674096faa DIFF: https://github.com/llvm/llvm-project/commit/29b141740d263f11c8e1d8490522ed7674096faa.diff LOG: [RISCV] Rename sifive-p870 -> sifive-p870-d (#199077) This matches the name on SiFive's website. Added: clang/test/Driver/print-enabled-extensions/riscv-sifive-p870-d.c Modified: clang/test/Driver/riscv-cpus.c clang/test/Misc/target-invalid-cpu-note/riscv.c llvm/docs/ReleaseNotes.md llvm/lib/Target/RISCV/RISCVProcessors.td llvm/test/Transforms/LoopUnroll/RISCV/vector.ll llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-load.ll llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-store.ll llvm/test/tools/llvm-mca/RISCV/SiFiveP800/atomic.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/floating-point.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/integer.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/mul-div.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/arithmetic.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/bitwise.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/comparison.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/conversion.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/fma.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/fp.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/mask.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/minmax.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/mul-div.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/permutation.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/reduction.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vle-vse-vlm.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vlse-vsse.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vlseg-vsseg.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vlxe-vsxe.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvbb.s llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvbc.s llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvbc.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvkg.s llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvkned.s llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvknhb.s llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvksed.s llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvksh.s llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zba.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zbb.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zbs.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfa.s llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfh.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfhmin.test llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zicond.test Removed: clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c ################################################################################ diff --git a/clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c b/clang/test/Driver/print-enabled-extensions/riscv-sifive-p870-d.c similarity index 98% rename from clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c rename to clang/test/Driver/print-enabled-extensions/riscv-sifive-p870-d.c index c7a9d80554f9c..6d8ccc4291b29 100644 --- a/clang/test/Driver/print-enabled-extensions/riscv-sifive-p870.c +++ b/clang/test/Driver/print-enabled-extensions/riscv-sifive-p870-d.c @@ -1,5 +1,5 @@ // REQUIRES: riscv-registered-target -// RUN: %clang --target=riscv64 -mcpu=sifive-p870 --print-enabled-extensions | FileCheck %s +// RUN: %clang --target=riscv64 -mcpu=sifive-p870-d --print-enabled-extensions | FileCheck %s // CHECK: Extensions enabled for the given RISC-V target // CHECK-EMPTY: diff --git a/clang/test/Driver/riscv-cpus.c b/clang/test/Driver/riscv-cpus.c index 5ca33d91452e0..99a4c0601b41b 100644 --- a/clang/test/Driver/riscv-cpus.c +++ b/clang/test/Driver/riscv-cpus.c @@ -570,10 +570,10 @@ // MCPU-SIFIVE-P670-SAME: "-target-feature" "+zvkt" // MCPU-SIFIVE-P670-SAME: "-target-abi" "lp64d" -// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p870 | FileCheck -check-prefix=MCPU-SIFIVE-P870 %s -// MCPU-SIFIVE-P870: "-target-cpu" "sifive-p870" -// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-sifive-p870.c` -// MCPU-SIFIVE-P870-SAME: "-target-abi" "lp64d" +// RUN: %clang -target riscv64 -### -c %s 2>&1 -mcpu=sifive-p870-d | FileCheck -check-prefix=MCPU-SIFIVE-P870-D %s +// MCPU-SIFIVE-P870-D: "-target-cpu" "sifive-p870-d" +// COM: The list of extensions are tested in `test/Driver/print-enabled-extensions/riscv-sifive-p870-d.c` +// MCPU-SIFIVE-P870-D-SAME: "-target-abi" "lp64d" // RUN: %clang -target riscv32 -### -c %s 2>&1 -mcpu=rp2350-hazard3 | FileCheck -check-prefix=MCPU-HAZARD3 %s // MCPU-HAZARD3: "-target-cpu" "rp2350-hazard3" diff --git a/clang/test/Misc/target-invalid-cpu-note/riscv.c b/clang/test/Misc/target-invalid-cpu-note/riscv.c index 5223d1f968b8f..234cc82a2bab6 100644 --- a/clang/test/Misc/target-invalid-cpu-note/riscv.c +++ b/clang/test/Misc/target-invalid-cpu-note/riscv.c @@ -41,7 +41,7 @@ // RISCV64-SAME: {{^}}, sifive-p470 // RISCV64-SAME: {{^}}, sifive-p550 // RISCV64-SAME: {{^}}, sifive-p670 -// RISCV64-SAME: {{^}}, sifive-p870 +// RISCV64-SAME: {{^}}, sifive-p870-d // RISCV64-SAME: {{^}}, sifive-s21 // RISCV64-SAME: {{^}}, sifive-s51 // RISCV64-SAME: {{^}}, sifive-s54 @@ -110,7 +110,7 @@ // TUNE-RISCV64-SAME: {{^}}, sifive-p470 // TUNE-RISCV64-SAME: {{^}}, sifive-p550 // TUNE-RISCV64-SAME: {{^}}, sifive-p670 -// TUNE-RISCV64-SAME: {{^}}, sifive-p870 +// TUNE-RISCV64-SAME: {{^}}, sifive-p870-d // TUNE-RISCV64-SAME: {{^}}, sifive-s21 // TUNE-RISCV64-SAME: {{^}}, sifive-s51 // TUNE-RISCV64-SAME: {{^}}, sifive-s54 diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md index aa0b158c8a73b..fc462fd796229 100644 --- a/llvm/docs/ReleaseNotes.md +++ b/llvm/docs/ReleaseNotes.md @@ -213,6 +213,7 @@ Makes programs 10x faster by doing Special New Thing. * Adds experimental assembler support for the 'Zvvfmm` (RISC-V Floating-Point Matrix Multiply-Accumulate) extension. * Adds support for 'Ziccid' (Instruction/Data Coherence and Consistency) extension. * Adds experimental assembler support for the `Xqccmt` (Qualcomm 16-bit Table Jump) vendor extension. +* `-mcpu=sifive-870` has been renamed `-mcpu=sifive-p870-d`. ### Changes to the WebAssembly Backend diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td index b72fd969be9dc..d7869e12afb56 100644 --- a/llvm/lib/Target/RISCV/RISCVProcessors.td +++ b/llvm/lib/Target/RISCV/RISCVProcessors.td @@ -589,29 +589,29 @@ def SIFIVE_P670 : RISCVProcessorModel<"sifive-p670", SiFiveP600Model, TuneVXRMPipelineFlush, TunePostRAScheduler]>; -def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", SiFiveP800Model, - !listconcat(RVA23U64Features, - [FeatureStdExtZama16b, - FeatureStdExtZfh, - FeatureStdExtZifencei, - FeatureStdExtZkr, - FeatureStdExtZvfbfmin, - FeatureStdExtZvfbfwma, - FeatureStdExtZvfh, - FeatureStdExtZvknc, - FeatureStdExtZvkng, - FeatureStdExtZvksc, - FeatureStdExtZvksg, - FeatureStdExtZvl128b, - FeatureUnalignedScalarMem, - FeatureUnalignedVectorMem]), - [TuneNoDefaultUnroll, - TuneConditionalCompressedMoveFusion, - TuneLUIADDIFusion, - TuneAUIPCADDIFusion, - TuneNoSinkSplatOperands, - TuneVXRMPipelineFlush, - TunePostRAScheduler]>; +def SIFIVE_P870_D : RISCVProcessorModel<"sifive-p870-d", SiFiveP800Model, + !listconcat(RVA23U64Features, + [FeatureStdExtZama16b, + FeatureStdExtZfh, + FeatureStdExtZifencei, + FeatureStdExtZkr, + FeatureStdExtZvfbfmin, + FeatureStdExtZvfbfwma, + FeatureStdExtZvfh, + FeatureStdExtZvknc, + FeatureStdExtZvkng, + FeatureStdExtZvksc, + FeatureStdExtZvksg, + FeatureStdExtZvl128b, + FeatureUnalignedScalarMem, + FeatureUnalignedVectorMem]), + [TuneNoDefaultUnroll, + TuneConditionalCompressedMoveFusion, + TuneLUIADDIFusion, + TuneAUIPCADDIFusion, + TuneNoSinkSplatOperands, + TuneVXRMPipelineFlush, + TunePostRAScheduler]>; def SYNTACORE_SCR1_BASE : RISCVProcessorModel<"syntacore-scr1-base", SyntacoreSCR1Model, diff --git a/llvm/test/Transforms/LoopUnroll/RISCV/vector.ll b/llvm/test/Transforms/LoopUnroll/RISCV/vector.ll index b441f42f267af..2c834748c79d7 100644 --- a/llvm/test/Transforms/LoopUnroll/RISCV/vector.ll +++ b/llvm/test/Transforms/LoopUnroll/RISCV/vector.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 ; RUN: opt -p loop-unroll -mtriple riscv64 -mattr=+v,+f -S %s | FileCheck %s --check-prefixes=COMMON,CHECK -; RUN: opt -p loop-unroll -mtriple=riscv64 -mcpu=sifive-p870 -S %s | FileCheck %s --check-prefixes=COMMON,SIFIVE +; RUN: opt -p loop-unroll -mtriple=riscv64 -mcpu=sifive-p870-d -S %s | FileCheck %s --check-prefixes=COMMON,SIFIVE define void @reverse(ptr %dst, ptr %src, i64 %len) { ; CHECK-LABEL: define void @reverse( diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-load.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-load.ll index 3229a788e33d2..6220e493f85ca 100644 --- a/llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-load.ll +++ b/llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-load.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=riscv64 -mcpu=sifive-p870 -passes=slp-vectorizer -S -slp-revec -slp-threshold=-100 %s | FileCheck %s +; RUN: opt -mtriple=riscv64 -mcpu=sifive-p870-d -passes=slp-vectorizer -S -slp-revec -slp-threshold=-100 %s | FileCheck %s ; Base case of strided load, implicitly is widened define void @widened_strided_load(ptr %in0, ptr %out0) { diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-store.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-store.ll index 47b806acb437a..52bf39eca76a7 100644 --- a/llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-store.ll +++ b/llvm/test/Transforms/SLPVectorizer/RISCV/revec-strided-store.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt -mtriple=riscv64 -mcpu=sifive-p870 -passes=slp-vectorizer -S -slp-revec -slp-threshold=-100 %s | FileCheck %s +; RUN: opt -mtriple=riscv64 -mcpu=sifive-p870-d -passes=slp-vectorizer -S -slp-revec -slp-threshold=-100 %s | FileCheck %s ; Strided load into strided store define void @strided_load_and_store(ptr %in, ptr %out) { diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/atomic.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/atomic.test index 9d3ab0402e4f1..10fa11e2edd53 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/atomic.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/atomic.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../Inputs/atomic.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../Inputs/atomic.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/floating-point.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/floating-point.test index 1d13d1f5d96b7..a9b7590e7318b 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/floating-point.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/floating-point.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../Inputs/floating-point.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../Inputs/floating-point.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/integer.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/integer.test index 4f0e0d69bebb8..fdc739b940665 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/integer.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/integer.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../Inputs/integer.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../Inputs/integer.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/mul-div.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/mul-div.test index 64f2dcb614b5c..011618d4346ba 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/mul-div.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/mul-div.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../Inputs/mul-div.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../Inputs/mul-div.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/arithmetic.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/arithmetic.test index f5eed96313766..691af97871ba4 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/arithmetic.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/arithmetic.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/arithmetic.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/arithmetic.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/bitwise.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/bitwise.test index 6d0cd0d9c4922..880fd9ed19cec 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/bitwise.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/bitwise.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/bitwise.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/bitwise.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/comparison.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/comparison.test index 430f61f1b6b00..22b8e4d1a430b 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/comparison.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/comparison.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/comparison.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/comparison.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/conversion.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/conversion.test index 7db0acce9e010..76e4a8d0171b0 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/conversion.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/conversion.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/conversion.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/conversion.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/fma.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/fma.test index 292cfbd3d0a71..9e952fd07599a 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/fma.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/fma.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/fma.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/fma.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/fp.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/fp.test index 2ccd46d1df45f..ca9b6b75438d1 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/fp.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/fp.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/fp.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/fp.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/mask.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/mask.test index 9d582d494d6db..7611747fa8711 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/mask.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/mask.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/mask.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/mask.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/minmax.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/minmax.test index b2d81b50e81e2..826debf12c539 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/minmax.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/minmax.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/minmax.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/minmax.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/mul-div.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/mul-div.test index 0cb64e70c64d2..068e1209d6ab2 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/mul-div.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/mul-div.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/mul-div.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/mul-div.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/permutation.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/permutation.test index 9a21127e71329..ac15343a80782 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/permutation.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/permutation.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/permutation.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/permutation.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/reduction.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/reduction.test index 74b763311afaf..19cc1214ec21a 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/reduction.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/reduction.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/reduction.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/reduction.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vle-vse-vlm.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vle-vse-vlm.test index 4c06f495f095b..950cf3ecedb19 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vle-vse-vlm.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vle-vse-vlm.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vle-vse-vlm.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vle-vse-vlm.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vlse-vsse.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vlse-vsse.test index cc14f295dffbb..393ae378de1e1 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vlse-vsse.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vlse-vsse.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlse-vsse.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlse-vsse.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vlseg-vsseg.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vlseg-vsseg.test index 77a02b570a072..5c71e3a542b7a 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vlseg-vsseg.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vlseg-vsseg.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlseg-vsseg.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlseg-vsseg.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vlxe-vsxe.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vlxe-vsxe.test index e4fffe7253683..9edc8ac082d58 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vlxe-vsxe.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/vlxe-vsxe.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlxe-vsxe.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/vlxe-vsxe.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvbb.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvbb.s index a2cf112b09e3c..a40d786a377aa 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvbb.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvbb.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full < %s | FileCheck %s vsetvli zero, zero, e8, mf8, tu, mu vandn.vv v4, v8, v12 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvbc.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvbc.s index a0ace32cc4eaf..7e80be292cbc5 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvbc.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvbc.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full < %s | FileCheck %s # These instructions only work with e64 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvbc.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvbc.test index 919dbedd28a0d..5d7c968648273 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvbc.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvbc.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/zvbc.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../../Inputs/rvv/zvbc.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvkg.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvkg.s index ae2880e4c8697..a5e3c8add2ce1 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvkg.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvkg.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full < %s | FileCheck %s vsetvli zero, zero, e8, mf8, tu, mu vghsh.vv v4, v8, v12 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvkned.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvkned.s index c0c935e855b73..ad8483ec3f02d 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvkned.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvkned.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full < %s | FileCheck %s # These instructions only support e32 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvknhb.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvknhb.s index fa9c9f6f4e680..63471ff6fca62 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvknhb.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvknhb.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full < %s | FileCheck %s # Worst case for vsha2ms should be that of LMUL=8 and SEW=64. vsha2ms.vv v4, v8, v12 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvksed.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvksed.s index 392c6efa82db7..0bb0b81ec115f 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvksed.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvksed.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full < %s | FileCheck %s # These instructions only support e32 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvksh.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvksh.s index 9dc2aef567805..6b121a765d291 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvksh.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/rvv/zvksh.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full < %s | FileCheck %s # These instructions only support e32 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zba.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zba.test index 8e3c3496fa437..7c2d92e9eeb62 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zba.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zba.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../Inputs/zba.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../Inputs/zba.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zbb.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zbb.test index 000481201699a..ebb13ed27583c 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zbb.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zbb.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../Inputs/zbb.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../Inputs/zbb.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zbs.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zbs.test index f7243a7615f5d..cda84f45ff1d5 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zbs.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zbs.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../Inputs/zbs.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../Inputs/zbs.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfa.s b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfa.s index 2bc5cc197be95..5ed8bee48954e 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfa.s +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfa.s @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full < %s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full < %s | FileCheck %s fli.h fa5, nan fli.s fa5, nan diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfh.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfh.test index 9a8ebdd205916..e92aeb354d083 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfh.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfh.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../Inputs/zfh.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../Inputs/zfh.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfhmin.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfhmin.test index 6f53906c8fa14..979e63b9ae46f 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfhmin.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zfhmin.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../Inputs/zfhmin.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../Inputs/zfhmin.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 diff --git a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zicond.test b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zicond.test index c0ca4e7d49b4a..70f10b378dbe3 100644 --- a/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zicond.test +++ b/llvm/test/tools/llvm-mca/RISCV/SiFiveP800/zicond.test @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py -# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870 -iterations=1 -instruction-tables=full %p/../Inputs/zicond.s | FileCheck %s +# RUN: llvm-mca -mtriple=riscv64 -mcpu=sifive-p870-d -iterations=1 -instruction-tables=full %p/../Inputs/zicond.s | FileCheck %s # CHECK: Resources: # CHECK-NEXT: [0] - SiFiveP800Branch:2 SiFiveP800IEXQ4, SiFiveP800IEXQ5 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
