================
@@ -54,7 +54,9 @@ SPIRVSubtarget::SPIRVSubtarget(const Triple &TT, const
std::string &CPU,
const std::string &FS,
const SPIRVTargetMachine &TM)
: SPIRVGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS),
- PointerSize(TM.getPointerSizeInBits(/* AS= */ 0)),
+ PointerSize(TM.getPointerSizeInBits(
+ /* AS= */ storageClassToAddressSpace(SPIRV::StorageClass::Generic,
----------------
AlexVlx wrote:
Right, this is fleshed out in a separate change that tweaks the DL for AMDGCN
flavoured SPIR-V. There's two things to consider here:
1. I am relatively certain that the intent here was to match what other targets
do, but other targets use 0 as `Generic` / `Flat` / ptr-that-just-works,
whereas for SPIR-V 0 is `Function` (`private`), which is rather quaint
considering that has constrained semantics that make it a poor candidate for
the one-pointer-that-defines-all;
2. In concrete terms, if we switch the DL to follow the AMDGPU one (which has
certain benefits as we pick up weirder ASes there in the future), 0 has 32-bit
sized addresses (for reasons of optimisation, amongst others), so this would
just break things as it'd set the default pointer size to 32-bits.
It seems (but I could be wrong) safe to do as it's NFC for anyone but us.
Furthermore, it hardens things in the face of future changes (assume e.g. we
just flip / change the AS map for vanilla SPIR-V; yes, any change there would
just be around matching other targets in what regards AS0:) ). It appears
desirable to have as few magic constants as possible.
https://github.com/llvm/llvm-project/pull/199376
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