================
@@ -2244,51 +2273,51 @@ void 
AArch64DAGToDAGISel::SelectMultiVectorLutiLane(SDNode *Node,
   if (!ImmToReg<AArch64::ZT0, 0>(Node->getOperand(2), ZtValue))
     return;
 
-  SDValue Chain = Node->getOperand(0);
-  SDValue Ops[] = {ZtValue, Node->getOperand(3), Node->getOperand(4), Chain};
-  SDLoc DL(Node);
-  EVT VT = Node->getValueType(0);
-
-  SDNode *Instruction =
-      CurDAG->getMachineNode(Opc, DL, {MVT::Untyped, MVT::Other}, Ops);
-  SDValue SuperReg = SDValue(Instruction, 0);
+  SmallVector<SDValue, 4> Ops = {ZtValue, Node->getOperand(3),
+                                 Node->getOperand(4), Node->getOperand(0)};
+  EmitMultiVectorLutiLane(Node, NumOutVecs, Opc, Ops);
+}
 
-  for (unsigned I = 0; I < NumOutVecs; ++I)
-    ReplaceUses(SDValue(Node, I), CurDAG->getTargetExtractSubreg(
-                                      AArch64::zsub0 + I, DL, VT, SuperReg));
+void AArch64DAGToDAGISel::SelectMultiVectorLutiLaneTuple(SDNode *Node,
+                                                         unsigned NumOutVecs,
+                                                         unsigned Opc,
+                                                         uint32_t MaxImm) {
+  auto *Imm = dyn_cast<ConstantSDNode>(Node->getOperand(5));
+  if (Imm && Imm->getZExtValue() > MaxImm)
+    return;
 
-  // Copy chain
-  unsigned ChainIdx = NumOutVecs;
-  ReplaceUses(SDValue(Node, ChainIdx), SDValue(Instruction, 1));
-  CurDAG->RemoveDeadNode(Node);
+  SmallVector<SDValue, 4> Ops = {
+      createZTuple({Node->getOperand(1), Node->getOperand(2)}),
+      createZTuple({Node->getOperand(3), Node->getOperand(4)}),
+      Node->getOperand(5),
+  };
+  EmitMultiVectorLutiLane(Node, NumOutVecs, Opc, Ops);
 }
 
 void AArch64DAGToDAGISel::SelectMultiVectorLuti(SDNode *Node,
                                                 unsigned NumOutVecs,
-                                                unsigned Opc) {
+                                                unsigned Opc,
+                                                unsigned NumInVecs) {
   SDValue ZtValue;
   if (!ImmToReg<AArch64::ZT0, 0>(Node->getOperand(2), ZtValue))
     return;
 
-  SDValue Chain = Node->getOperand(0);
-  SDValue Ops[] = {ZtValue,
-                   createZMulTuple({Node->getOperand(3), Node->getOperand(4)}),
-                   Chain};
+  SmallVector<SDValue, 4> Regs(Node->ops().slice(3, NumInVecs));
+  SDValue ZTuple = NumInVecs == 2 ? createZMulTuple(Regs) : createZTuple(Regs);
----------------
jthackray wrote:

Thanks, done.

https://github.com/llvm/llvm-project/pull/187046
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