================
@@ -30,16 +30,41 @@ CIRGenFunction::emitRISCVBuiltinExpr(unsigned builtinID,
const CallExpr *e) {
StringRef intrinsicName;
mlir::Type returnType = convertType(e->getType());
+ mlir::Location loc = getLoc(e->getSourceRange());
llvm::SmallVector<mlir::Value> ops;
// `iceArguments` is a bitmap indicating whether the argument at the i-th bit
// is required to be a constant integer expression.
unsigned iceArguments = 0;
ASTContext::GetBuiltinTypeError error;
getContext().GetBuiltinType(builtinID, error, &iceArguments);
- assert(error == ASTContext::GE_None && "Should not codegen an error");
- for (auto [idx, arg] : llvm::enumerate(e->arguments()))
+
+ // RVV vector builtins use a special type overload mechanism (no type
string).
+ if (error == ASTContext::GE_Missing_type) {
+ // Vector intrinsics don't have a type string.
+ assert(builtinID >= clang::RISCV::FirstRVVBuiltin &&
+ builtinID <= clang::RISCV::LastRVVBuiltin);
+ iceArguments = 0;
+ if (builtinID == RISCVVector::BI__builtin_rvv_vget_v ||
+ builtinID == RISCVVector::BI__builtin_rvv_vset_v)
+ iceArguments = 1 << 1;
+ } else {
+ assert(error == ASTContext::GE_None && "Unexpected error");
+ }
+
+ for (auto [idx, arg] : llvm::enumerate(e->arguments())) {
+ // Handle aggregate argument, namely RVV tuple types in segment load/store
+ if (hasAggregateEvaluationKind(arg->getType())) {
+ LValue lv = emitAggExprToLValue(arg);
+ ops.push_back(builder.createLoad(loc, lv.getAddress()));
+ continue;
+ }
ops.push_back(emitScalarOrConstFoldImmArg(iceArguments, idx, arg));
+ }
+
+ // TODO: Handle ManualCodegen.
+ bool hasCirManualCodegen = false;
+ int PolicyAttrs = 0;
----------------
andykaylor wrote:
Nit: CIR coding style wants this to be camelCase. Is it reasonable to change
that in the tablegen'd code or does it get mixed with LLVM IR codegen code?
https://github.com/llvm/llvm-project/pull/199889
_______________________________________________
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
