llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang Author: Vicky Nguyen (iamvickynguyen) <details> <summary>Changes</summary> Related to https://github.com/llvm/llvm-project/issues/185382 CIR lowering for vector-shift-right-and-accumulate (https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-right-and-accumulate) Port tests from `clang/test/CodeGen/AArch64/neon_intrinsics.c` to `clang/test/CodeGen/AArch64/neon/intrinsics.c` --- Patch is 27.07 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/200630.diff 3 Files Affected: - (modified) clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp (+27-7) - (modified) clang/test/CodeGen/AArch64/neon-intrinsics.c (-255) - (modified) clang/test/CodeGen/AArch64/neon/intrinsics.c (+308) ``````````diff diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 0b4581e13f0a1..a06b76d453d48 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -2602,8 +2602,28 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, return builder.getConstInt(loc, builder.getUInt64Ty(), 0); return builder.createShiftRight(loc, ops[0], shiftAmt); } - case NEON::BI__builtin_neon_vsrad_n_s64: - case NEON::BI__builtin_neon_vsrad_n_u64: + case NEON::BI__builtin_neon_vsrad_n_s64: { + std::optional<llvm::APSInt> amt = + expr->getArg(2)->getIntegerConstantExpr(getContext()); + assert(amt && "Expected argument to be a constant"); + uint64_t shiftAmt = + std::min(static_cast<uint64_t>(63), amt->getZExtValue()); + mlir::Value shifted = + builder.createShiftRight(loc, ops[1], static_cast<unsigned>(shiftAmt)); + return builder.createAdd(loc, ops[0], shifted); + } + case NEON::BI__builtin_neon_vsrad_n_u64: { + std::optional<llvm::APSInt> amt = + expr->getArg(2)->getIntegerConstantExpr(getContext()); + assert(amt && "Expected argument to be a constant"); + uint64_t shiftAmt = amt->getZExtValue(); + // Right-shifting an unsigned value by its size yields 0, so a + 0 = a. + if (shiftAmt == 64) + return ops[0]; + mlir::Value shifted = + builder.createShiftRight(loc, ops[1], static_cast<unsigned>(shiftAmt)); + return builder.createAdd(loc, ops[0], shifted); + } case NEON::BI__builtin_neon_vqdmlalh_lane_s16: case NEON::BI__builtin_neon_vqdmlalh_laneq_s16: case NEON::BI__builtin_neon_vqdmlslh_lane_s16: @@ -2978,11 +2998,11 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, /*shift=*/0, /*rightshift=*/false); } case NEON::BI__builtin_neon_vsra_n_v: - case NEON::BI__builtin_neon_vsraq_n_v: - cgm.errorNYI(expr->getSourceRange(), - std::string("unimplemented AArch64 builtin call: ") + - getContext().BuiltinInfo.getName(builtinID)); - return mlir::Value{}; + case NEON::BI__builtin_neon_vsraq_n_v: { + ops[0] = builder.createBitcast(ops[0], ty); + ops[1] = emitNeonRShiftImm(*this, ops[1], ops[2], ty, usgn, loc); + return builder.createAdd(loc, ops[0], ops[1]); + } case NEON::BI__builtin_neon_vrsra_n_v: case NEON::BI__builtin_neon_vrsraq_n_v: { intrName = usgn ? "aarch64.neon.urshl" : "aarch64.neon.srshl"; diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index 6c514cee8fdc2..c4eac89e78bc1 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -5107,200 +5107,6 @@ float64x2_t test_vmulxq_f64(float64x2_t a, float64x2_t b) { return vmulxq_f64(a, b); } -// CHECK-LABEL: define dso_local <8 x i8> @test_vsra_n_s8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSRA_N:%.*]] = ashr <8 x i8> [[B]], splat (i8 3) -// CHECK-NEXT: [[TMP0:%.*]] = add <8 x i8> [[A]], [[VSRA_N]] -// CHECK-NEXT: ret <8 x i8> [[TMP0]] -// -int8x8_t test_vsra_n_s8(int8x8_t a, int8x8_t b) { - return vsra_n_s8(a, b, 3); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vsra_n_s16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VSRA_N:%.*]] = ashr <4 x i16> [[TMP3]], splat (i16 3) -// CHECK-NEXT: [[TMP4:%.*]] = add <4 x i16> [[TMP2]], [[VSRA_N]] -// CHECK-NEXT: ret <4 x i16> [[TMP4]] -// -int16x4_t test_vsra_n_s16(int16x4_t a, int16x4_t b) { - return vsra_n_s16(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vsra_n_s32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VSRA_N:%.*]] = ashr <2 x i32> [[TMP3]], splat (i32 3) -// CHECK-NEXT: [[TMP4:%.*]] = add <2 x i32> [[TMP2]], [[VSRA_N]] -// CHECK-NEXT: ret <2 x i32> [[TMP4]] -// -int32x2_t test_vsra_n_s32(int32x2_t a, int32x2_t b) { - return vsra_n_s32(a, b, 3); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vsraq_n_s8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSRA_N:%.*]] = ashr <16 x i8> [[B]], splat (i8 3) -// CHECK-NEXT: [[TMP0:%.*]] = add <16 x i8> [[A]], [[VSRA_N]] -// CHECK-NEXT: ret <16 x i8> [[TMP0]] -// -int8x16_t test_vsraq_n_s8(int8x16_t a, int8x16_t b) { - return vsraq_n_s8(a, b, 3); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vsraq_n_s16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK-NEXT: [[VSRA_N:%.*]] = ashr <8 x i16> [[TMP3]], splat (i16 3) -// CHECK-NEXT: [[TMP4:%.*]] = add <8 x i16> [[TMP2]], [[VSRA_N]] -// CHECK-NEXT: ret <8 x i16> [[TMP4]] -// -int16x8_t test_vsraq_n_s16(int16x8_t a, int16x8_t b) { - return vsraq_n_s16(a, b, 3); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vsraq_n_s32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// CHECK-NEXT: [[VSRA_N:%.*]] = ashr <4 x i32> [[TMP3]], splat (i32 3) -// CHECK-NEXT: [[TMP4:%.*]] = add <4 x i32> [[TMP2]], [[VSRA_N]] -// CHECK-NEXT: ret <4 x i32> [[TMP4]] -// -int32x4_t test_vsraq_n_s32(int32x4_t a, int32x4_t b) { - return vsraq_n_s32(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vsraq_n_s64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// CHECK-NEXT: [[VSRA_N:%.*]] = ashr <2 x i64> [[TMP3]], splat (i64 3) -// CHECK-NEXT: [[TMP4:%.*]] = add <2 x i64> [[TMP2]], [[VSRA_N]] -// CHECK-NEXT: ret <2 x i64> [[TMP4]] -// -int64x2_t test_vsraq_n_s64(int64x2_t a, int64x2_t b) { - return vsraq_n_s64(a, b, 3); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vsra_n_u8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]], <8 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSRA_N:%.*]] = lshr <8 x i8> [[B]], splat (i8 3) -// CHECK-NEXT: [[TMP0:%.*]] = add <8 x i8> [[A]], [[VSRA_N]] -// CHECK-NEXT: ret <8 x i8> [[TMP0]] -// -uint8x8_t test_vsra_n_u8(uint8x8_t a, uint8x8_t b) { - return vsra_n_u8(a, b, 3); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vsra_n_u16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]], <4 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> -// CHECK-NEXT: [[VSRA_N:%.*]] = lshr <4 x i16> [[TMP3]], splat (i16 3) -// CHECK-NEXT: [[TMP4:%.*]] = add <4 x i16> [[TMP2]], [[VSRA_N]] -// CHECK-NEXT: ret <4 x i16> [[TMP4]] -// -uint16x4_t test_vsra_n_u16(uint16x4_t a, uint16x4_t b) { - return vsra_n_u16(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vsra_n_u32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]], <2 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> -// CHECK-NEXT: [[VSRA_N:%.*]] = lshr <2 x i32> [[TMP3]], splat (i32 3) -// CHECK-NEXT: [[TMP4:%.*]] = add <2 x i32> [[TMP2]], [[VSRA_N]] -// CHECK-NEXT: ret <2 x i32> [[TMP4]] -// -uint32x2_t test_vsra_n_u32(uint32x2_t a, uint32x2_t b) { - return vsra_n_u32(a, b, 3); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vsraq_n_u8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]], <16 x i8> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VSRA_N:%.*]] = lshr <16 x i8> [[B]], splat (i8 3) -// CHECK-NEXT: [[TMP0:%.*]] = add <16 x i8> [[A]], [[VSRA_N]] -// CHECK-NEXT: ret <16 x i8> [[TMP0]] -// -uint8x16_t test_vsraq_n_u8(uint8x16_t a, uint8x16_t b) { - return vsraq_n_u8(a, b, 3); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vsraq_n_u16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]], <8 x i16> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> -// CHECK-NEXT: [[VSRA_N:%.*]] = lshr <8 x i16> [[TMP3]], splat (i16 3) -// CHECK-NEXT: [[TMP4:%.*]] = add <8 x i16> [[TMP2]], [[VSRA_N]] -// CHECK-NEXT: ret <8 x i16> [[TMP4]] -// -uint16x8_t test_vsraq_n_u16(uint16x8_t a, uint16x8_t b) { - return vsraq_n_u16(a, b, 3); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vsraq_n_u32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]], <4 x i32> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> -// CHECK-NEXT: [[VSRA_N:%.*]] = lshr <4 x i32> [[TMP3]], splat (i32 3) -// CHECK-NEXT: [[TMP4:%.*]] = add <4 x i32> [[TMP2]], [[VSRA_N]] -// CHECK-NEXT: ret <4 x i32> [[TMP4]] -// -uint32x4_t test_vsraq_n_u32(uint32x4_t a, uint32x4_t b) { - return vsraq_n_u32(a, b, 3); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vsraq_n_u64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]], <2 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> -// CHECK-NEXT: [[VSRA_N:%.*]] = lshr <2 x i64> [[TMP3]], splat (i64 3) -// CHECK-NEXT: [[TMP4:%.*]] = add <2 x i64> [[TMP2]], [[VSRA_N]] -// CHECK-NEXT: ret <2 x i64> [[TMP4]] -// -uint64x2_t test_vsraq_n_u64(uint64x2_t a, uint64x2_t b) { - return vsraq_n_u64(a, b, 3); -} - // CHECK-LABEL: define dso_local <8 x i8> @test_vqshlu_n_s8( // CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -14423,67 +14229,6 @@ uint64_t test_vcaltd_f64(float64_t a, float64_t b) { return (uint64_t)vcaltd_f64(a, b); } -// CHECK-LABEL: define dso_local i64 @test_vsrad_n_s64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHRD_N:%.*]] = ashr i64 [[B]], 63 -// CHECK-NEXT: [[TMP0:%.*]] = add i64 [[A]], [[SHRD_N]] -// CHECK-NEXT: ret i64 [[TMP0]] -// -int64_t test_vsrad_n_s64(int64_t a, int64_t b) { - return (int64_t)vsrad_n_s64(a, b, 63); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vsra_n_s64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// CHECK-NEXT: [[VSRA_N:%.*]] = ashr <1 x i64> [[TMP3]], splat (i64 1) -// CHECK-NEXT: [[TMP4:%.*]] = add <1 x i64> [[TMP2]], [[VSRA_N]] -// CHECK-NEXT: ret <1 x i64> [[TMP4]] -// -int64x1_t test_vsra_n_s64(int64x1_t a, int64x1_t b) { - return vsra_n_s64(a, b, 1); -} - -// CHECK-LABEL: define dso_local i64 @test_vsrad_n_u64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[SHRD_N:%.*]] = lshr i64 [[B]], 63 -// CHECK-NEXT: [[TMP0:%.*]] = add i64 [[A]], [[SHRD_N]] -// CHECK-NEXT: ret i64 [[TMP0]] -// -uint64_t test_vsrad_n_u64(uint64_t a, uint64_t b) { - return (uint64_t)vsrad_n_u64(a, b, 63); -} - -// CHECK-LABEL: define dso_local i64 @test_vsrad_n_u64_2( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: ret i64 [[A]] -// -uint64_t test_vsrad_n_u64_2(uint64_t a, uint64_t b) { - return (uint64_t)vsrad_n_u64(a, b, 64); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vsra_n_u64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]], <1 x i64> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <1 x i64> -// CHECK-NEXT: [[VSRA_N:%.*]] = lshr <1 x i64> [[TMP3]], splat (i64 1) -// CHECK-NEXT: [[TMP4:%.*]] = add <1 x i64> [[TMP2]], [[VSRA_N]] -// CHECK-NEXT: ret <1 x i64> [[TMP4]] -// -uint64x1_t test_vsra_n_u64(uint64x1_t a, uint64x1_t b) { - return vsra_n_u64(a, b, 1); -} - // CHECK-LABEL: define dso_local i8 @test_vqshlb_n_s8( // CHECK-SAME: i8 noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index c783ea57deff0..efa2691ef611e 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -4441,6 +4441,314 @@ uint64_t test_vcvtd_n_u64_f64(float64_t a) { return (uint64_t)vcvtd_n_u64_f64(a, 64); } +//===------------------------------------------------------===// +// 2.1.3.2.3 Vector shift right and accumulate +// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-right-and-accumulate +//===------------------------------------------------------===// + +// ALL-LABEL: @test_vsra_n_s8( +int8x8_t test_vsra_n_s8(int8x8_t a, int8x8_t b) { +// CIR: cir.vec.splat +// CIR: cir.shift(right, +// CIR: cir.add + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[VSRA_N:%.*]] = ashr <8 x i8> [[B]], splat (i8 3) +// LLVM: [[TMP0:%.*]] = add <8 x i8> [[A]], [[VSRA_N]] +// LLVM: ret <8 x i8> [[TMP0]] + return vsra_n_s8(a, b, 3); +} + +// ALL-LABEL: @test_vsra_n_s16( +int16x4_t test_vsra_n_s16(int16x4_t a, int16x4_t b) { +// CIR: cir.cast bitcast +// CIR: cir.vec.splat +// CIR: cir.shift(right, +// CIR: cir.add + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> +// LLVM-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> +// LLVM-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <4 x i16> +// LLVM-NEXT: [[VSRA_N:%.*]] = ashr <4 x i16> [[TMP3]], splat (i16 3) +// LLVM-NEXT: [[TMP4:%.*]] = add <4 x i16> [[TMP2]], [[VSRA_N]] +// LLVM: ret <4 x i16> [[TMP4]] + return vsra_n_s16(a, b, 3); +} + +// ALL-LABEL: @test_vsra_n_s32( +int32x2_t test_vsra_n_s32(int32x2_t a, int32x2_t b) { +// CIR: cir.cast bitcast +// CIR: cir.vec.splat +// CIR: cir.shift(right, +// CIR: cir.add + +// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i32> [[B]] to <8 x i8> +// LLVM-NEXT: [[TMP2:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> +// LLVM-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP1]] to <2 x i32> +// LLVM-NEXT: [[VSRA_N:%.*]] = ashr <2 x i32> [[TMP3]], splat (i32 3) +// LLVM-NEXT: [[TMP4:%.*]] = add <2 x i32> [[TMP2]], [[VSRA_N]] +// LLVM: ret <2 x i32> [[TMP4]] + return vsra_n_s32(a, b, 3); +} + +// ALL-LABEL: @test_vsraq_n_s8( +int8x16_t test_vsraq_n_s8(int8x16_t a, int8x16_t b) { +// CIR: cir.vec.splat +// CIR: cir.shift(right, +// CIR: cir.add + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[VSRA_N:%.*]] = ashr <16 x i8> [[B]], splat (i8 3) +// LLVM: [[TMP0:%.*]] = add <16 x i8> [[A]], [[VSRA_N]] +// LLVM: ret <16 x i8> [[TMP0]] + return vsraq_n_s8(a, b, 3); +} + +// ALL-LABEL: @test_vsraq_n_s16( +int16x8_t test_vsraq_n_s16(int16x8_t a, int16x8_t b) { +// CIR: cir.cast bitcast +// CIR: cir.vec.splat +// CIR: cir.shift(right, +// CIR: cir.add + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> +// LLVM-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> +// LLVM-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <8 x i16> +// LLVM-NEXT: [[VSRA_N:%.*]] = ashr <8 x i16> [[TMP3]], splat (i16 3) +// LLVM-NEXT: [[TMP4:%.*]] = add <8 x i16> [[TMP2]], [[VSRA_N]] +// LLVM: ret <8 x i16> [[TMP4]] + return vsraq_n_s16(a, b, 3); +} + +// ALL-LABEL: @test_vsraq_n_s32( +int32x4_t test_vsraq_n_s32(int32x4_t a, int32x4_t b) { +// CIR: cir.cast bitcast +// CIR: cir.vec.splat +// CIR: cir.shift(right, +// CIR: cir.add + +// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i32> [[B]] to <16 x i8> +// LLVM-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> +// LLVM-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> +// LLVM-NEXT: [[VSRA_N:%.*]] = ashr <4 x i32> [[TMP3]], splat (i32 3) +// LLVM-NEXT: [[TMP4:%.*]] = add <4 x i32> [[TMP2]], [[VSRA_N]] +// LLVM: ret <4 x i32> [[TMP4]] + return vsraq_n_s32(a, b, 3); +} + +// ALL-LABEL: @test_vsraq_n_s64( +int64x2_t test_vsraq_n_s64(int64x2_t a, int64x2_t b) { +// CIR: cir.cast bitcast +// CIR: cir.vec.splat +// CIR: cir.shift(right, +// CIR: cir.add + +// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> +// LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> +// LLVM-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> +// LLVM-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP1]] to <2 x i64> +// LLVM-NEXT: [[VSRA_N:%.*]] = ashr <2 x i64> [[TMP3]], splat (i64 3) +// LLVM-NEXT: [[TMP4:%.*]] = add <2 x i64> [[TMP2]], [[VSRA_N]] +// LLVM: ret <2 x i64> [[TMP4]] + return vsraq_n_s64(a, b, 3); +} + +// ALL-LABEL: @test_vsra_n_u8( +uint8x8_t test_vsra_n_u8(uint8x8_t a, u... [truncated] `````````` </details> https://github.com/llvm/llvm-project/pull/200630 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
