https://github.com/Ko496-glitch updated https://github.com/llvm/llvm-project/pull/199153
>From 3db9ed41e03169e4160d64c4a6f877a8855c9762 Mon Sep 17 00:00:00 2001 From: Kartik Ohlan <[email protected]> Date: Thu, 21 May 2026 22:35:27 -0400 Subject: [PATCH 1/4] added implementation vqshl/vqshlq -- vqshlu/vqshluq --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 23 +++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index a06b76d453d48..f65cb8a09e244 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -878,10 +878,6 @@ static mlir::Value emitCommonNeonBuiltinExpr( case NEON::BI__builtin_neon_vqdmulh_laneq_v: case NEON::BI__builtin_neon_vqrdmulhq_laneq_v: case NEON::BI__builtin_neon_vqrdmulh_laneq_v: - case NEON::BI__builtin_neon_vqshl_n_v: - case NEON::BI__builtin_neon_vqshlq_n_v: - case NEON::BI__builtin_neon_vqshlu_n_v: - case NEON::BI__builtin_neon_vqshluq_n_v: case NEON::BI__builtin_neon_vrecpe_v: case NEON::BI__builtin_neon_vrecpeq_v: case NEON::BI__builtin_neon_vrsqrte_v: @@ -911,6 +907,25 @@ static mlir::Value emitCommonNeonBuiltinExpr( std::string("unimplemented AArch64 builtin call: ") + ctx.BuiltinInfo.getName(builtinID)); return mlir::Value{}; + case NEON::BI__builtin_neon_vqshlu_n_v: + case NEON::BI__builtin_neon_vqshluq_n_v: { + llvm::StringRef intrName = "aarch.neon.sqshlu"; + return emitNeonCall(cgf.cgm, cgf.getBuilder(), + {ty, getSignChangedVectorType(cgf.getBuilder(), ty)}, + ops, intrName, ty, loc, + /*isConstrainedFPIntrinsic=*/false, + /*shift=*/1); + } + case NEON::BI__builtin_neon_vqshl_n_v: + case NEON::BI__builtin_neon_vqshlq_n_v: { + llvm::StringRef intrName = + usgn ? "aarch64.neon.uqshl" : "aarch64.neon.sqshl"; + return emitNeonCall( + cgf.cgm, cgf.getBuilder(), + {ty, usgn ? getSignChangedVectorType(cgf.getBuilder(), ty) : ty}, ops, + intrName, ty, loc, /*isConstrainedFPIntrinsic=*/false, + /*shift=*/1); + } case NEON::BI__builtin_neon_vshl_n_v: case NEON::BI__builtin_neon_vshlq_n_v: return emitCommonNeonShift(cgf.getBuilder(), loc, vTy, ops[0], ops[1], >From 1193e7a3c834dcb7cb9ff7b2a88dcc0209c5674c Mon Sep 17 00:00:00 2001 From: Kartik Ohlan <[email protected]> Date: Tue, 2 Jun 2026 21:31:47 -0700 Subject: [PATCH 2/4] added revisions --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 42 ++++++++++--------- 1 file changed, 23 insertions(+), 19 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index f65cb8a09e244..08f49888de651 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -878,6 +878,29 @@ static mlir::Value emitCommonNeonBuiltinExpr( case NEON::BI__builtin_neon_vqdmulh_laneq_v: case NEON::BI__builtin_neon_vqrdmulhq_laneq_v: case NEON::BI__builtin_neon_vqrdmulh_laneq_v: + cgf.cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AArch64 builtin call: ") + + cgf.getContext().BuiltinInfo.getName(builtinID)); + return mlir::Value{}; + case NEON::BI__builtin_neon_vqshl_n_v: + case NEON::BI__builtin_neon_vqshlq_n_v: { + llvm::StringRef intrName = + usgn ? "aarch64.neon.uqshl" : "aarch64.neon.sqshl"; + return emitNeonCall( + cgf.cgm, cgf.getBuilder(), + {ty, usgn ? getSignChangedVectorType(cgf.getBuilder(), ty) : ty}, ops, + intrName, ty, loc, /*isConstrainedFPIntrinsic=*/false, + /*shift=*/1); + } + case NEON::BI__builtin_neon_vqshlu_n_v: + case NEON::BI__builtin_neon_vqshluq_n_v: { + llvm::StringRef intrName = "aarch.neon.sqshlu"; + return emitNeonCall(cgf.cgm, cgf.getBuilder(), + {ty, getSignChangedVectorType(cgf.getBuilder(), ty)}, + ops, intrName, ty, loc, + /*isConstrainedFPIntrinsic=*/false, + /*shift=*/1); + } case NEON::BI__builtin_neon_vrecpe_v: case NEON::BI__builtin_neon_vrecpeq_v: case NEON::BI__builtin_neon_vrsqrte_v: @@ -907,25 +930,6 @@ static mlir::Value emitCommonNeonBuiltinExpr( std::string("unimplemented AArch64 builtin call: ") + ctx.BuiltinInfo.getName(builtinID)); return mlir::Value{}; - case NEON::BI__builtin_neon_vqshlu_n_v: - case NEON::BI__builtin_neon_vqshluq_n_v: { - llvm::StringRef intrName = "aarch.neon.sqshlu"; - return emitNeonCall(cgf.cgm, cgf.getBuilder(), - {ty, getSignChangedVectorType(cgf.getBuilder(), ty)}, - ops, intrName, ty, loc, - /*isConstrainedFPIntrinsic=*/false, - /*shift=*/1); - } - case NEON::BI__builtin_neon_vqshl_n_v: - case NEON::BI__builtin_neon_vqshlq_n_v: { - llvm::StringRef intrName = - usgn ? "aarch64.neon.uqshl" : "aarch64.neon.sqshl"; - return emitNeonCall( - cgf.cgm, cgf.getBuilder(), - {ty, usgn ? getSignChangedVectorType(cgf.getBuilder(), ty) : ty}, ops, - intrName, ty, loc, /*isConstrainedFPIntrinsic=*/false, - /*shift=*/1); - } case NEON::BI__builtin_neon_vshl_n_v: case NEON::BI__builtin_neon_vshlq_n_v: return emitCommonNeonShift(cgf.getBuilder(), loc, vTy, ops[0], ops[1], >From ee9efe08e6547f74bbe30544ca79613ed2a6e961 Mon Sep 17 00:00:00 2001 From: Kartik Ohlan <[email protected]> Date: Tue, 2 Jun 2026 22:00:26 -0700 Subject: [PATCH 3/4] adding test-cases --- clang/test/CodeGen/AArch64/neon-intrinsics.c | 22 -------------------- clang/test/CodeGen/AArch64/neon/intrinsics.c | 22 ++++++++++++++++++++ 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index c4eac89e78bc1..aa01013d12615 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -14263,16 +14263,6 @@ int32_t test_vqshls_n_s32(int32_t a) { return (int32_t)vqshls_n_s32(a, 31); } -// CHECK-LABEL: define dso_local <8 x i8> @test_vqshl_n_s8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHL_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> [[A]], <8 x i8> zeroinitializer) -// CHECK-NEXT: ret <8 x i8> [[VQSHL_N]] -// -int8x8_t test_vqshl_n_s8(int8x8_t a) { - return vqshl_n_s8(a, 0); -} - // CHECK-LABEL: define dso_local <16 x i8> @test_vqshlq_n_s8( // CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -14283,18 +14273,6 @@ int8x16_t test_vqshlq_n_s8(int8x16_t a) { return vqshlq_n_s8(a, 0); } -// CHECK-LABEL: define dso_local <4 x i16> @test_vqshl_n_s16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[VQSHL_N]], <4 x i16> zeroinitializer) -// CHECK-NEXT: ret <4 x i16> [[VQSHL_N1]] -// -int16x4_t test_vqshl_n_s16(int16x4_t a) { - return vqshl_n_s16(a, 0); -} - // CHECK-LABEL: define dso_local <8 x i16> @test_vqshlq_n_s16( // CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index efa2691ef611e..2a5b65238d898 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -459,6 +459,28 @@ float64_t test_vmaxvq_f64(float64x2_t a) { // TODO: Implement the remaining intrinsics from this group. //===------------------------------------------------------===// +// ALL-LABEL: @test_vqshl_n_s8( +int8x8_t test_vqshl_n_s8(int8x8_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl" + + // LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]]) + // LLVM: [[VQSHL_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshl.v8i8(<8 x i8> [[A]], <8 x i8> zeroinitializer) + // LLVM: ret <8 x i8> [[VQSHL_N]] + return vqshl_n_s8(a, 0); +} + +// ALL-LABEL: @test_vqshl_n_s16( +int16x4_t test_vqshl_n_s16(int16x4_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl" + // + // LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> + // LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> + // LLVM: [[VQSHL_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshl.v4i16(<4 x i16> [[VQSHL_N]], <4 x i16> zeroinitializer) + // LLVM: ret <4 x i16> [[VQSHL_N1]] + return vqshl_n_s16(a, 0); +} + // ALL-LABEL: @test_vqshlud_n_s64( int64_t test_vqshlud_n_s64(int64_t a) { // CIR: [[CONST:%.*]] = cir.const #cir.int<63> : !s64i >From 525a45687b36e894e0fccd567f1dcc7564b5e1b3 Mon Sep 17 00:00:00 2001 From: Kartik Ohlan <[email protected]> Date: Sun, 7 Jun 2026 21:09:50 -0700 Subject: [PATCH 4/4] added more test --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 2 +- clang/test/CodeGen/AArch64/neon-intrinsics.c | 254 ------------------ clang/test/CodeGen/AArch64/neon/intrinsics.c | 254 ++++++++++++++++++ 3 files changed, 255 insertions(+), 255 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 08f49888de651..bfab17b0c5baf 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -894,7 +894,7 @@ static mlir::Value emitCommonNeonBuiltinExpr( } case NEON::BI__builtin_neon_vqshlu_n_v: case NEON::BI__builtin_neon_vqshluq_n_v: { - llvm::StringRef intrName = "aarch.neon.sqshlu"; + llvm::StringRef intrName = "aarch64.neon.sqshlu"; return emitNeonCall(cgf.cgm, cgf.getBuilder(), {ty, getSignChangedVectorType(cgf.getBuilder(), ty)}, ops, intrName, ty, loc, diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index aa01013d12615..c4a8b18228ea1 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -5107,86 +5107,6 @@ float64x2_t test_vmulxq_f64(float64x2_t a, float64x2_t b) { return vmulxq_f64(a, b); } -// CHECK-LABEL: define dso_local <8 x i8> @test_vqshlu_n_s8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHLU_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> [[A]], <8 x i8> splat (i8 3)) -// CHECK-NEXT: ret <8 x i8> [[VQSHLU_N]] -// -uint8x8_t test_vqshlu_n_s8(int8x8_t a) { - return vqshlu_n_s8(a, 3); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vqshlu_n_s16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> [[VQSHLU_N]], <4 x i16> splat (i16 3)) -// CHECK-NEXT: ret <4 x i16> [[VQSHLU_N1]] -// -uint16x4_t test_vqshlu_n_s16(int16x4_t a) { - return vqshlu_n_s16(a, 3); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vqshlu_n_s32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> [[VQSHLU_N]], <2 x i32> splat (i32 3)) -// CHECK-NEXT: ret <2 x i32> [[VQSHLU_N1]] -// -uint32x2_t test_vqshlu_n_s32(int32x2_t a) { - return vqshlu_n_s32(a, 3); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vqshluq_n_s8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHLU_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 3)) -// CHECK-NEXT: ret <16 x i8> [[VQSHLU_N]] -// -uint8x16_t test_vqshluq_n_s8(int8x16_t a) { - return vqshluq_n_s8(a, 3); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vqshluq_n_s16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16> [[VQSHLU_N]], <8 x i16> splat (i16 3)) -// CHECK-NEXT: ret <8 x i16> [[VQSHLU_N1]] -// -uint16x8_t test_vqshluq_n_s16(int16x8_t a) { - return vqshluq_n_s16(a, 3); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vqshluq_n_s32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32> [[VQSHLU_N]], <4 x i32> splat (i32 3)) -// CHECK-NEXT: ret <4 x i32> [[VQSHLU_N1]] -// -uint32x4_t test_vqshluq_n_s32(int32x4_t a) { - return vqshluq_n_s32(a, 3); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vqshluq_n_s64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> [[VQSHLU_N]], <2 x i64> splat (i64 3)) -// CHECK-NEXT: ret <2 x i64> [[VQSHLU_N1]] -// -uint64x2_t test_vqshluq_n_s64(int64x2_t a) { - return vqshluq_n_s64(a, 3); -} - // CHECK-LABEL: define dso_local <8 x i8> @test_vshrn_n_s16( // CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -14263,156 +14183,6 @@ int32_t test_vqshls_n_s32(int32_t a) { return (int32_t)vqshls_n_s32(a, 31); } -// CHECK-LABEL: define dso_local <16 x i8> @test_vqshlq_n_s8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHL_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> [[A]], <16 x i8> zeroinitializer) -// CHECK-NEXT: ret <16 x i8> [[VQSHL_N]] -// -int8x16_t test_vqshlq_n_s8(int8x16_t a) { - return vqshlq_n_s8(a, 0); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vqshlq_n_s16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> [[VQSHL_N]], <8 x i16> zeroinitializer) -// CHECK-NEXT: ret <8 x i16> [[VQSHL_N1]] -// -int16x8_t test_vqshlq_n_s16(int16x8_t a) { - return vqshlq_n_s16(a, 0); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vqshl_n_s32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> [[VQSHL_N]], <2 x i32> zeroinitializer) -// CHECK-NEXT: ret <2 x i32> [[VQSHL_N1]] -// -int32x2_t test_vqshl_n_s32(int32x2_t a) { - return vqshl_n_s32(a, 0); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vqshlq_n_s32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> [[VQSHL_N]], <4 x i32> zeroinitializer) -// CHECK-NEXT: ret <4 x i32> [[VQSHL_N1]] -// -int32x4_t test_vqshlq_n_s32(int32x4_t a) { - return vqshlq_n_s32(a, 0); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vqshlq_n_s64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> [[VQSHL_N]], <2 x i64> zeroinitializer) -// CHECK-NEXT: ret <2 x i64> [[VQSHL_N1]] -// -int64x2_t test_vqshlq_n_s64(int64x2_t a) { - return vqshlq_n_s64(a, 0); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vqshl_n_u8( -// CHECK-SAME: <8 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHL_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[A]], <8 x i8> zeroinitializer) -// CHECK-NEXT: ret <8 x i8> [[VQSHL_N]] -// -uint8x8_t test_vqshl_n_u8(uint8x8_t a) { - return vqshl_n_u8(a, 0); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vqshlq_n_u8( -// CHECK-SAME: <16 x i8> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VQSHL_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> [[A]], <16 x i8> zeroinitializer) -// CHECK-NEXT: ret <16 x i8> [[VQSHL_N]] -// -uint8x16_t test_vqshlq_n_u8(uint8x16_t a) { - return vqshlq_n_u8(a, 0); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vqshl_n_u16( -// CHECK-SAME: <4 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[VQSHL_N]], <4 x i16> zeroinitializer) -// CHECK-NEXT: ret <4 x i16> [[VQSHL_N1]] -// -uint16x4_t test_vqshl_n_u16(uint16x4_t a) { - return vqshl_n_u16(a, 0); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vqshlq_n_u16( -// CHECK-SAME: <8 x i16> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> [[VQSHL_N]], <8 x i16> zeroinitializer) -// CHECK-NEXT: ret <8 x i16> [[VQSHL_N1]] -// -uint16x8_t test_vqshlq_n_u16(uint16x8_t a) { - return vqshlq_n_u16(a, 0); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vqshl_n_u32( -// CHECK-SAME: <2 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> [[VQSHL_N]], <2 x i32> zeroinitializer) -// CHECK-NEXT: ret <2 x i32> [[VQSHL_N1]] -// -uint32x2_t test_vqshl_n_u32(uint32x2_t a) { - return vqshl_n_u32(a, 0); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vqshlq_n_u32( -// CHECK-SAME: <4 x i32> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> [[VQSHL_N]], <4 x i32> zeroinitializer) -// CHECK-NEXT: ret <4 x i32> [[VQSHL_N1]] -// -uint32x4_t test_vqshlq_n_u32(uint32x4_t a) { - return vqshlq_n_u32(a, 0); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vqshlq_n_u64( -// CHECK-SAME: <2 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> [[VQSHL_N]], <2 x i64> zeroinitializer) -// CHECK-NEXT: ret <2 x i64> [[VQSHL_N1]] -// -uint64x2_t test_vqshlq_n_u64(uint64x2_t a) { - return vqshlq_n_u64(a, 0); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vqshl_n_s64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> [[VQSHL_N]], <1 x i64> splat (i64 1)) -// CHECK-NEXT: ret <1 x i64> [[VQSHL_N1]] -// -int64x1_t test_vqshl_n_s64(int64x1_t a) { - return vqshl_n_s64(a, 1); -} - // CHECK-LABEL: define dso_local i8 @test_vqshlb_n_u8( // CHECK-SAME: i8 noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -14447,18 +14217,6 @@ uint32_t test_vqshls_n_u32(uint32_t a) { return (uint32_t)vqshls_n_u32(a, 31); } -// CHECK-LABEL: define dso_local <1 x i64> @test_vqshl_n_u64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VQSHL_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> [[VQSHL_N]], <1 x i64> splat (i64 1)) -// CHECK-NEXT: ret <1 x i64> [[VQSHL_N1]] -// -uint64x1_t test_vqshl_n_u64(uint64x1_t a) { - return vqshl_n_u64(a, 1); -} - // CHECK-LABEL: define dso_local i8 @test_vqshlub_n_s8( // CHECK-SAME: i8 noundef [[A:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -14493,18 +14251,6 @@ int32_t test_vqshlus_n_s32(int32_t a) { return (int32_t)vqshlus_n_s32(a, 31); } -// CHECK-LABEL: define dso_local <1 x i64> @test_vqshlu_n_s64( -// CHECK-SAME: <1 x i64> noundef [[A:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> -// CHECK-NEXT: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> -// CHECK-NEXT: [[VQSHLU_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshlu.v1i64(<1 x i64> [[VQSHLU_N]], <1 x i64> splat (i64 1)) -// CHECK-NEXT: ret <1 x i64> [[VQSHLU_N1]] -// -uint64x1_t test_vqshlu_n_s64(int64x1_t a) { - return vqshlu_n_s64(a, 1); -} - // CHECK-LABEL: define dso_local i64 @test_vslid_n_s64( // CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index 2a5b65238d898..bcbde72ebe40a 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -459,6 +459,260 @@ float64_t test_vmaxvq_f64(float64x2_t a) { // TODO: Implement the remaining intrinsics from this group. //===------------------------------------------------------===// +// ALL-LABEL: {{.*}}@test_vqshl_n_s32( +int32x2_t test_vqshl_n_s32(int32x2_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl" + + // LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> + // LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> + // LLVM: [[VQSHL_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshl.v2i32(<2 x i32> [[VQSHL_N]], <2 x i32> zeroinitializer) + // LLVM: ret <2 x i32> [[VQSHL_N1]] + return vqshl_n_s32(a, 0); +} + +// ALL-LABEL: {{.*}}@test_vqshl_n_s64( +int64x1_t test_vqshl_n_s64(int64x1_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl" + + // LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> + // LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> + // LLVM: [[VQSHL_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshl.v1i64(<1 x i64> [[VQSHL_N]], <1 x i64> {{.*}}) + // LLVM: ret <1 x i64> [[VQSHL_N1]] + return vqshl_n_s64(a, 1); +} + +// ALL-LABEL: {{.*}}@test_vqshlq_n_s8( +int8x16_t test_vqshlq_n_s8(int8x16_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl" + + // LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]]) + // LLVM: [[VQSHL_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshl.v16i8(<16 x i8> [[A]], <16 x i8> zeroinitializer) + // LLVM: ret <16 x i8> [[VQSHL_N]] + return vqshlq_n_s8(a, 0); +} + +// ALL-LABEL: {{.*}}@test_vqshlq_n_s16( +int16x8_t test_vqshlq_n_s16(int16x8_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl" + + // LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> + // LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> + // LLVM: [[VQSHL_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshl.v8i16(<8 x i16> [[VQSHL_N]], <8 x i16> zeroinitializer) + // LLVM: ret <8 x i16> [[VQSHL_N1]] + return vqshlq_n_s16(a, 0); +} + +// ALL-LABEL: {{.*}}@test_vqshlq_n_s32( +int32x4_t test_vqshlq_n_s32(int32x4_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl" + + // LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> + // LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> + // LLVM: [[VQSHL_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshl.v4i32(<4 x i32> [[VQSHL_N]], <4 x i32> zeroinitializer) + // LLVM: ret <4 x i32> [[VQSHL_N1]] + return vqshlq_n_s32(a, 0); +} + +// ALL-LABEL: {{.*}}@test_vqshlq_n_s64( +int64x2_t test_vqshlq_n_s64(int64x2_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl" + + // LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> + // LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> + // LLVM: [[VQSHL_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshl.v2i64(<2 x i64> [[VQSHL_N]], <2 x i64> zeroinitializer) + // LLVM: ret <2 x i64> [[VQSHL_N1]] + return vqshlq_n_s64(a, 0); +} + +// ALL-LABEL: {{.*}}@test_vqshl_n_u8( +uint8x8_t test_vqshl_n_u8(uint8x8_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl" + + // LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]]) + // LLVM: [[VQSHL_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.uqshl.v8i8(<8 x i8> [[A]], <8 x i8> zeroinitializer) + // LLVM: ret <8 x i8> [[VQSHL_N]] + return vqshl_n_u8(a, 0); +} + +// ALL-LABEL: {{.*}}@test_vqshl_n_u16( +uint16x4_t test_vqshl_n_u16(uint16x4_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl" + + // LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> + // LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> + // LLVM: [[VQSHL_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.uqshl.v4i16(<4 x i16> [[VQSHL_N]], <4 x i16> zeroinitializer) + // LLVM: ret <4 x i16> [[VQSHL_N1]] + return vqshl_n_u16(a, 0); +} + +// ALL-LABEL: {{.*}}@test_vqshl_n_u32( +uint32x2_t test_vqshl_n_u32(uint32x2_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl" + + // LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> + // LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> + // LLVM: [[VQSHL_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.uqshl.v2i32(<2 x i32> [[VQSHL_N]], <2 x i32> zeroinitializer) + // LLVM: ret <2 x i32> [[VQSHL_N1]] + return vqshl_n_u32(a, 0); +} + +// ALL-LABEL: {{.*}}@test_vqshl_n_u64( +uint64x1_t test_vqshl_n_u64(uint64x1_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl" + + // LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> + // LLVM: [[VQSHL_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> + // LLVM: [[VQSHL_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.uqshl.v1i64(<1 x i64> [[VQSHL_N]], <1 x i64> {{.*}}) + // LLVM: ret <1 x i64> [[VQSHL_N1]] + return vqshl_n_u64(a, 1); +} + +// ALL-LABEL: {{.*}}@test_vqshlq_n_u8( +uint8x16_t test_vqshlq_n_u8(uint8x16_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl" + + // LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]]) + // LLVM: [[VQSHL_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.uqshl.v16i8(<16 x i8> [[A]], <16 x i8> zeroinitializer) + // LLVM: ret <16 x i8> [[VQSHL_N]] + return vqshlq_n_u8(a, 0); +} + +// ALL-LABEL: {{.*}}@test_vqshlq_n_u16( +uint16x8_t test_vqshlq_n_u16(uint16x8_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl" + + // LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> + // LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> + // LLVM: [[VQSHL_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.uqshl.v8i16(<8 x i16> [[VQSHL_N]], <8 x i16> zeroinitializer) + // LLVM: ret <8 x i16> [[VQSHL_N1]] + return vqshlq_n_u16(a, 0); +} + +// ALL-LABEL: {{.*}}@test_vqshlq_n_u32( +uint32x4_t test_vqshlq_n_u32(uint32x4_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl" + + // LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> + // LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> + // LLVM: [[VQSHL_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.uqshl.v4i32(<4 x i32> [[VQSHL_N]], <4 x i32> zeroinitializer) + // LLVM: ret <4 x i32> [[VQSHL_N1]] + return vqshlq_n_u32(a, 0); +} + +// ALL-LABEL: {{.*}}@test_vqshlq_n_u64( +uint64x2_t test_vqshlq_n_u64(uint64x2_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.uqshl" + + // LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> + // LLVM: [[VQSHL_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> + // LLVM: [[VQSHL_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.uqshl.v2i64(<2 x i64> [[VQSHL_N]], <2 x i64> zeroinitializer) + // LLVM: ret <2 x i64> [[VQSHL_N1]] + return vqshlq_n_u64(a, 0); +} + +// ALL-LABEL: {{.*}}@test_vqshlu_n_s8( +uint8x8_t test_vqshlu_n_s8(int8x8_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshlu" + + // LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]]) + // LLVM: [[VQSHLU_N:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqshlu.v8i8(<8 x i8> [[A]], <8 x i8> {{.*}}) + // LLVM: ret <8 x i8> [[VQSHLU_N]] + return vqshlu_n_s8(a, 3); +} + +// ALL-LABEL: {{.*}}@test_vqshlu_n_s16( +uint16x4_t test_vqshlu_n_s16(int16x4_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshlu" + + // LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> + // LLVM: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <4 x i16> + // LLVM: [[VQSHLU_N1:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqshlu.v4i16(<4 x i16> [[VQSHLU_N]], <4 x i16> {{.*}}) + // LLVM: ret <4 x i16> [[VQSHLU_N1]] + return vqshlu_n_s16(a, 3); +} + +// ALL-LABEL: {{.*}}@test_vqshlu_n_s32( +uint32x2_t test_vqshlu_n_s32(int32x2_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshlu" + + // LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <2 x i32> [[A]] to <8 x i8> + // LLVM: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <2 x i32> + // LLVM: [[VQSHLU_N1:%.*]] = call <2 x i32> @llvm.aarch64.neon.sqshlu.v2i32(<2 x i32> [[VQSHLU_N]], <2 x i32> {{.*}}) + // LLVM: ret <2 x i32> [[VQSHLU_N1]] + return vqshlu_n_s32(a, 3); +} + +// ALL-LABEL: {{.*}}@test_vqshlu_n_s64( +uint64x1_t test_vqshlu_n_s64(int64x1_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshlu" + + // LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> + // LLVM: [[VQSHLU_N:%.*]] = bitcast <8 x i8> [[TMP0]] to <1 x i64> + // LLVM: [[VQSHLU_N1:%.*]] = call <1 x i64> @llvm.aarch64.neon.sqshlu.v1i64(<1 x i64> [[VQSHLU_N]], <1 x i64> {{.*}}) + // LLVM: ret <1 x i64> [[VQSHLU_N1]] + return vqshlu_n_s64(a, 1); +} + +// ALL-LABEL: {{.*}}@test_vqshluq_n_s8( +uint8x16_t test_vqshluq_n_s8(int8x16_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshlu" + + // LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]]) + // LLVM: [[VQSHLU_N:%.*]] = call <16 x i8> @llvm.aarch64.neon.sqshlu.v16i8(<16 x i8> [[A]], <16 x i8> splat (i8 3)) + // LLVM: ret <16 x i8> [[VQSHLU_N]] + return vqshluq_n_s8(a, 3); +} + +// ALL-LABEL: {{.*}}@test_vqshluq_n_s16( +uint16x8_t test_vqshluq_n_s16(int16x8_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshlu" + + // LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> + // LLVM: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <8 x i16> + // LLVM: [[VQSHLU_N1:%.*]] = call <8 x i16> @llvm.aarch64.neon.sqshlu.v8i16(<8 x i16> [[VQSHLU_N]], <8 x i16> splat (i16 3)) + // LLVM: ret <8 x i16> [[VQSHLU_N1]] + return vqshluq_n_s16(a, 3); +} + +// ALL-LABEL: {{.*}}@test_vqshluq_n_s32( +uint32x4_t test_vqshluq_n_s32(int32x4_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshlu" + + // LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <4 x i32> [[A]] to <16 x i8> + // LLVM: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <4 x i32> + // LLVM: [[VQSHLU_N1:%.*]] = call <4 x i32> @llvm.aarch64.neon.sqshlu.v4i32(<4 x i32> [[VQSHLU_N]], <4 x i32> splat (i32 3)) + // LLVM: ret <4 x i32> [[VQSHLU_N1]] + return vqshluq_n_s32(a, 3); +} + +// ALL-LABEL: {{.*}}@test_vqshluq_n_s64( +uint64x2_t test_vqshluq_n_s64(int64x2_t a) { + // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshlu" + + // LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> + // LLVM: [[VQSHLU_N:%.*]] = bitcast <16 x i8> [[TMP0]] to <2 x i64> + // LLVM: [[VQSHLU_N1:%.*]] = call <2 x i64> @llvm.aarch64.neon.sqshlu.v2i64(<2 x i64> [[VQSHLU_N]], <2 x i64> splat (i64 3)) + // LLVM: ret <2 x i64> [[VQSHLU_N1]] + return vqshluq_n_s64(a, 3); +} + // ALL-LABEL: @test_vqshl_n_s8( int8x8_t test_vqshl_n_s8(int8x8_t a) { // CIR: cir.call_llvm_intrinsic "aarch64.neon.sqshl" _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
