================
@@ -12435,13 +12434,23 @@ class BaseCAS<string order, string size,
RegisterClass RC>
let NP = 1;
}
-multiclass CompareAndSwap<bits<1> Acq, bits<1> Rel, string order> {
- let Sz = 0b00, Acq = Acq, Rel = Rel in def B : BaseCAS<order, "b", GPR32>;
- let Sz = 0b01, Acq = Acq, Rel = Rel in def H : BaseCAS<order, "h", GPR32>;
- let Sz = 0b10, Acq = Acq, Rel = Rel in def W : BaseCAS<order, "", GPR32>;
- let Sz = 0b11, Acq = Acq, Rel = Rel in def X : BaseCAS<order, "", GPR64>;
+multiclass CompareAndSwap_impl<bits<1> Acq, bits<1> Rel, string order,
list<Predicate> preds, string suffix> {
+ let Predicates = preds, Acq = Acq, Rel = Rel in {
+ let Sz = 0b00 in def "B" # suffix : BaseCAS<order, "b", GPR32>;
+ let Sz = 0b01 in def "H" # suffix : BaseCAS<order, "h", GPR32>;
+ let Sz = 0b10 in def "W" # suffix : BaseCAS<order, "", GPR32>;
+ let Sz = 0b11 in def "X" # suffix : BaseCAS<order, "", GPR64>;
+ }
}
+multiclass CompareAndSwap<bits<1> Acq, bits<1> Rel, string order>
+ : CompareAndSwap_impl<Acq, Rel, order, [HasLSE], "">;
+
+// For isCodeGenOnly use by MS intrinsics that must emit CAS* regardless
+// of the -march setting.
----------------
efriedma-quic wrote:
This will break if we generate assembly (-save-temps/-S): the parser will
refuse to parse illegal instructions. I guess we can make the Arm64AsmPrinter
generate explicit .arch_extension directives to fix this.
https://github.com/llvm/llvm-project/pull/202416
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