https://github.com/AmrDeveloper updated https://github.com/llvm/llvm-project/pull/202707
>From 1651678ee2e07778121529790b17b13ef2104784 Mon Sep 17 00:00:00 2001 From: Amr Hesham <[email protected]> Date: Tue, 9 Jun 2026 18:35:27 +0200 Subject: [PATCH 1/3] [CIR] Implement Unary inc for VectorType of int --- clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp | 18 ++++++++--- clang/test/CIR/CodeGenOpenCL/vector.cl | 36 ++++++++++++++++++++++ 2 files changed, 49 insertions(+), 5 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp index d8b7fa062b845..8448fb98417cd 100644 --- a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp @@ -614,6 +614,8 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> { mlir::Value value; mlir::Value input; + mlir::Location loc = cgf.getLoc(e->getSourceRange()); + int amount = e->isIncrementOp() ? 1 : -1; if (type->getAs<AtomicType>()) { cgf.cgm.errorNYI(e->getSourceRange(), "Atomic inc/dec"); @@ -683,16 +685,22 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> { value = cgf.getBuilder().createPtrStride(loc, value, numElts); } else { // For everything else, we can just do a simple increment. - mlir::Location loc = cgf.getLoc(e->getSourceRange()); - CIRGenBuilderTy &builder = cgf.getBuilder(); - int amount = e->isIncrementOp() ? 1 : -1; mlir::Value amt = builder.getSInt32(amount, loc); assert(!cir::MissingFeatures::sanitizers()); value = builder.createPtrStride(loc, value, amt); } } else if (type->isVectorType()) { - cgf.cgm.errorNYI(e->getSourceRange(), "Unary inc/dec vector"); - return {}; + if (type->hasIntegerRepresentation()) { + mlir::Type vecElemTy = + mlir::cast<cir::VectorType>(value.getType()).getElementType(); + cir::ConstantOp constAmt = builder.getConstInt(loc, vecElemTy, amount); + auto amtVec = + cir::VecSplatOp::create(builder, loc, value.getType(), constAmt); + value = builder.createAdd(loc, value, amtVec); + } else { + cgf.cgm.errorNYI(e->getSourceRange(), "Unary inc/dec vector of float"); + return {}; + } } else if (type->isRealFloatingType()) { CIRGenFunction::CIRGenFPOptionsRAII FPOptsRAII(cgf, e); diff --git a/clang/test/CIR/CodeGenOpenCL/vector.cl b/clang/test/CIR/CodeGenOpenCL/vector.cl index 7212ef22c026d..eb072233c433d 100644 --- a/clang/test/CIR/CodeGenOpenCL/vector.cl +++ b/clang/test/CIR/CodeGenOpenCL/vector.cl @@ -70,3 +70,39 @@ float4 vec_ternary_f4(int4 c, float4 a, float4 b) { // LLVM: %[[IS_NEG:.*]] = icmp slt <4 x i32> %[[COND:.*]], zeroinitializer // LLVM: %[[RESULT:.*]] = select <4 x i1> %[[IS_NEG]], <4 x float> %[[A:.*]], <4 x float> %[[B:.*]] // LLVM: ret <4 x float> %[[RESULT]] + +int4 vec_unary_inc(int4 a) { + ++a; + return a; +} + +// CIR: %[[A_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["a", init] +// CIR: %[[RET_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["__retval"] +// CIR: cir.store %{{.*}}, %[[A_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>> +// CIR: %[[TMP_A:.*]] = cir.load {{.*}} %[[A_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i> +// CIR: %[[CONST_1_VEC:.*]] = cir.const #cir.const_vector<[#cir.int<1> : !s32i, #cir.int<1> : !s32i, #cir.int<1> : !s32i, #cir.int<1> : !s32i]> : !cir.vector<4 x !s32i> +// CIR: %[[VEC_INC:.*]] = cir.add %[[TMP_A]], %[[CONST_1_VEC]] : !cir.vector<4 x !s32i> +// CIR: cir.store {{.*}} %[[VEC_INC]], %[[A_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>> +// CIR: %[[RESULT:.*]] = cir.load {{.*}} %[[A_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i> +// CIR: cir.store %[[RESULT]], %[[RET_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>> + +// LLVM: %[[VEC_INC:.*]] = add <4 x i32> %[[A:.*]], splat (i32 1) +// LLVM: ret <4 x i32> %[[VEC_INC]] + +int4 vec_unary_dec(int4 a) { + --a; + return a; +} + +// CIR: %[[A_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["a", init] +// CIR: %[[RET_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["__retval"] +// CIR: cir.store %{{.*}}, %[[A_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>> +// CIR: %[[TMP_A:.*]] = cir.load {{.*}} %[[A_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i> +// CIR: %[[CONST_N1_VEC:.*]] = cir.const #cir.const_vector<[#cir.int<-1> : !s32i, #cir.int<-1> : !s32i, #cir.int<-1> : !s32i, #cir.int<-1> : !s32i]> : !cir.vector<4 x !s32i> +// CIR: %[[VEC_DEC:.*]] = cir.add %[[TMP_A]], %[[CONST_N1_VEC]] : !cir.vector<4 x !s32i> +// CIR: cir.store {{.*}} %[[VEC_DEC]], %[[A_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>> +// CIR: %[[RESULT:.*]] = cir.load {{.*}} %[[A_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i> +// CIR: cir.store %[[RESULT]], %[[RET_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>> + +// LLVM: %[[VEC_DEC:.*]] = add <4 x i32> %[[A:.*]], splat (i32 -1) +// LLVM: ret <4 x i32> %[[VEC_DEC]] >From 94e14b0acb707a8dc1b7988d4b00a151f3ae22f2 Mon Sep 17 00:00:00 2001 From: Amr Hesham <[email protected]> Date: Wed, 10 Jun 2026 20:18:17 +0200 Subject: [PATCH 2/3] Address code review comments --- clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp index 8448fb98417cd..1777b6a1349a3 100644 --- a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp @@ -614,8 +614,6 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> { mlir::Value value; mlir::Value input; - mlir::Location loc = cgf.getLoc(e->getSourceRange()); - int amount = e->isIncrementOp() ? 1 : -1; if (type->getAs<AtomicType>()) { cgf.cgm.errorNYI(e->getSourceRange(), "Atomic inc/dec"); @@ -685,12 +683,16 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> { value = cgf.getBuilder().createPtrStride(loc, value, numElts); } else { // For everything else, we can just do a simple increment. + mlir::Location loc = cgf.getLoc(e->getSourceRange()); + int amount = e->isIncrementOp() ? 1 : -1; mlir::Value amt = builder.getSInt32(amount, loc); assert(!cir::MissingFeatures::sanitizers()); value = builder.createPtrStride(loc, value, amt); } } else if (type->isVectorType()) { if (type->hasIntegerRepresentation()) { + mlir::Location loc = cgf.getLoc(e->getSourceRange()); + int amount = e->isIncrementOp() ? 1 : -1; mlir::Type vecElemTy = mlir::cast<cir::VectorType>(value.getType()).getElementType(); cir::ConstantOp constAmt = builder.getConstInt(loc, vecElemTy, amount); >From d9c6ceb7e555dc0032793a529cbdec950ffcf3d8 Mon Sep 17 00:00:00 2001 From: Amr Hesham <[email protected]> Date: Wed, 10 Jun 2026 20:54:47 +0200 Subject: [PATCH 3/3] Use cir::Inc & cir::Dec --- clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp | 9 +-------- .../lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp | 10 ++++++++-- clang/test/CIR/CodeGenOpenCL/vector.cl | 14 ++++++-------- 3 files changed, 15 insertions(+), 18 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp index 1777b6a1349a3..6bad03f92bfc7 100644 --- a/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenExprScalar.cpp @@ -691,14 +691,7 @@ class ScalarExprEmitter : public StmtVisitor<ScalarExprEmitter, mlir::Value> { } } else if (type->isVectorType()) { if (type->hasIntegerRepresentation()) { - mlir::Location loc = cgf.getLoc(e->getSourceRange()); - int amount = e->isIncrementOp() ? 1 : -1; - mlir::Type vecElemTy = - mlir::cast<cir::VectorType>(value.getType()).getElementType(); - cir::ConstantOp constAmt = builder.getConstInt(loc, vecElemTy, amount); - auto amtVec = - cir::VecSplatOp::create(builder, loc, value.getType(), constAmt); - value = builder.createAdd(loc, value, amtVec); + value = emitIncOrDec(e, input, /*nsw=*/false); } else { cgf.cgm.errorNYI(e->getSourceRange(), "Unary inc/dec vector of float"); return {}; diff --git a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp index c7eccd2f19c19..d72b9e8cb9b68 100644 --- a/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp +++ b/clang/lib/CIR/Lowering/DirectToLLVM/LowerToLLVM.cpp @@ -2590,12 +2590,18 @@ template <typename CIROp, typename LLVMIntOp> static mlir::LogicalResult lowerIncDecOp(CIROp op, typename CIROp::Adaptor adaptor, mlir::ConversionPatternRewriter &rewriter) { - mlir::Type elementType = elementTypeIfVector(op.getType()); mlir::Type llvmType = adaptor.getInput().getType(); mlir::Location loc = op.getLoc(); auto maybeNSW = nswFlag(op.getNoSignedWrap()); - auto one = mlir::LLVM::ConstantOp::create(rewriter, loc, llvmType, 1); + mlir::LLVM::ConstantOp one; + if (mlir::isa<cir::VectorType>(op.getType())) { + mlir::DenseIntElementsAttr oneVec = mlir::DenseIntElementsAttr::get( + mlir::cast<mlir::ShapedType>(llvmType), 1); + one = mlir::LLVM::ConstantOp::create(rewriter, loc, llvmType, oneVec); + } else { + one = mlir::LLVM::ConstantOp::create(rewriter, loc, llvmType, 1); + } rewriter.replaceOpWithNewOp<LLVMIntOp>(op, adaptor.getInput(), one, maybeNSW); return mlir::success(); } diff --git a/clang/test/CIR/CodeGenOpenCL/vector.cl b/clang/test/CIR/CodeGenOpenCL/vector.cl index eb072233c433d..4013449cb49b2 100644 --- a/clang/test/CIR/CodeGenOpenCL/vector.cl +++ b/clang/test/CIR/CodeGenOpenCL/vector.cl @@ -76,12 +76,11 @@ int4 vec_unary_inc(int4 a) { return a; } -// CIR: %[[A_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["a", init] -// CIR: %[[RET_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["__retval"] +// CIR: %[[A_ADDR:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.vector<4 x !s32i>> +// CIR: %[[RET_ADDR:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<4 x !s32i>> // CIR: cir.store %{{.*}}, %[[A_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>> // CIR: %[[TMP_A:.*]] = cir.load {{.*}} %[[A_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i> -// CIR: %[[CONST_1_VEC:.*]] = cir.const #cir.const_vector<[#cir.int<1> : !s32i, #cir.int<1> : !s32i, #cir.int<1> : !s32i, #cir.int<1> : !s32i]> : !cir.vector<4 x !s32i> -// CIR: %[[VEC_INC:.*]] = cir.add %[[TMP_A]], %[[CONST_1_VEC]] : !cir.vector<4 x !s32i> +// CIR: %[[VEC_INC:.*]] = cir.inc %[[TMP_A]] : !cir.vector<4 x !s32i> // CIR: cir.store {{.*}} %[[VEC_INC]], %[[A_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>> // CIR: %[[RESULT:.*]] = cir.load {{.*}} %[[A_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i> // CIR: cir.store %[[RESULT]], %[[RET_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>> @@ -94,12 +93,11 @@ int4 vec_unary_dec(int4 a) { return a; } -// CIR: %[[A_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["a", init] -// CIR: %[[RET_ADDR:.*]] = cir.alloca !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>>, ["__retval"] +// CIR: %[[A_ADDR:.*]] = cir.alloca "a" {{.*}} init : !cir.ptr<!cir.vector<4 x !s32i>> +// CIR: %[[RET_ADDR:.*]] = cir.alloca "__retval" {{.*}} : !cir.ptr<!cir.vector<4 x !s32i>> // CIR: cir.store %{{.*}}, %[[A_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>> // CIR: %[[TMP_A:.*]] = cir.load {{.*}} %[[A_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i> -// CIR: %[[CONST_N1_VEC:.*]] = cir.const #cir.const_vector<[#cir.int<-1> : !s32i, #cir.int<-1> : !s32i, #cir.int<-1> : !s32i, #cir.int<-1> : !s32i]> : !cir.vector<4 x !s32i> -// CIR: %[[VEC_DEC:.*]] = cir.add %[[TMP_A]], %[[CONST_N1_VEC]] : !cir.vector<4 x !s32i> +// CIR: %[[VEC_DEC:.*]] = cir.dec %[[TMP_A]] : !cir.vector<4 x !s32i> // CIR: cir.store {{.*}} %[[VEC_DEC]], %[[A_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>> // CIR: %[[RESULT:.*]] = cir.load {{.*}} %[[A_ADDR]] : !cir.ptr<!cir.vector<4 x !s32i>>, !cir.vector<4 x !s32i> // CIR: cir.store %[[RESULT]], %[[RET_ADDR]] : !cir.vector<4 x !s32i>, !cir.ptr<!cir.vector<4 x !s32i>> _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
