llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT--> @llvm/pr-subscribers-clang-driver @llvm/pr-subscribers-backend-aarch64 Author: eastB233 <details> <summary>Changes</summary> This patch adds initial support for Hisilicon's hip12 core (Kunpeng 950 processor). For more information, see: https://www.huawei.com/en/news/2025/9/hc-xu-keynote-speech HIP12Model will come later. --- Full diff: https://github.com/llvm/llvm-project/pull/203446.diff 10 Files Affected: - (added) clang/test/Driver/aarch64-hip12.c (+13) - (added) clang/test/Driver/print-enabled-extensions/aarch64-hip12.c (+72) - (modified) clang/test/Misc/target-invalid-cpu-note/aarch64.c (+1) - (modified) llvm/lib/Target/AArch64/AArch64Processors.td (+28-1) - (modified) llvm/lib/Target/AArch64/AArch64Subtarget.cpp (+6) - (modified) llvm/lib/TargetParser/Host.cpp (+1) - (modified) llvm/test/CodeGen/AArch64/cpus.ll (+1) - (modified) llvm/unittests/Target/AArch64/AArch64CacheLineSizeTest.cpp (+1) - (modified) llvm/unittests/TargetParser/Host.cpp (+4) - (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+2-1) ``````````diff diff --git a/clang/test/Driver/aarch64-hip12.c b/clang/test/Driver/aarch64-hip12.c new file mode 100644 index 0000000000000..c810cc26a9952 --- /dev/null +++ b/clang/test/Driver/aarch64-hip12.c @@ -0,0 +1,13 @@ +// RUN: %clang --target=aarch64 -mcpu=hip12 -### -c %s 2>&1 | FileCheck -check-prefix=HIP12 %s +// RUN: %clang --target=aarch64 -mlittle-endian -mcpu=hip12 -### -c %s 2>&1 | FileCheck -check-prefix=HIP12 %s +// RUN: %clang --target=aarch64 -mtune=hip12 -### -c %s 2>&1 | FileCheck -check-prefix=HIP12-TUNE %s +// RUN: %clang --target=aarch64 -mlittle-endian -mtune=hip12 -### -c %s 2>&1 | FileCheck -check-prefix=HIP12-TUNE %s +// HIP12: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "hip12" +// HIP12-TUNE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" + +// RUN: %clang --target=arm64 -mcpu=hip12 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-HIP12 %s +// RUN: %clang --target=arm64 -mlittle-endian -mcpu=hip12 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-HIP12 %s +// RUN: %clang --target=arm64 -mtune=hip12 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-HIP12-TUNE %s +// RUN: %clang --target=arm64 -mlittle-endian -mtune=hip12 -### -c %s 2>&1 | FileCheck -check-prefix=ARM64-HIP12-TUNE %s +// ARM64-HIP12: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "hip12" +// ARM64-HIP12-TUNE: "-cc1"{{.*}} "-triple" "arm64{{.*}}" "-target-cpu" "generic" diff --git a/clang/test/Driver/print-enabled-extensions/aarch64-hip12.c b/clang/test/Driver/print-enabled-extensions/aarch64-hip12.c new file mode 100644 index 0000000000000..8469e912aa4db --- /dev/null +++ b/clang/test/Driver/print-enabled-extensions/aarch64-hip12.c @@ -0,0 +1,72 @@ +// REQUIRES: aarch64-registered-target +// RUN: %clang --target=aarch64 --print-enabled-extensions -mcpu=hip12 | FileCheck --strict-whitespace --implicit-check-not=FEAT_ %s + +// CHECK: Extensions enabled for the given AArch64 target +// CHECK-EMPTY: +// CHECK-NEXT: Architecture Feature(s) Description +// CHECK-NEXT: FEAT_AES, FEAT_PMULL Enable AES support +// CHECK-NEXT: FEAT_AMUv1 Enable Armv8.4-A Activity Monitors extension +// CHECK-NEXT: FEAT_AMUv1p1 Enable Armv8.6-A Activity Monitors Virtualization support +// CHECK-NEXT: FEAT_AdvSIMD Enable Advanced SIMD instructions +// CHECK-NEXT: FEAT_BF16 Enable BFloat16 Extension +// CHECK-NEXT: FEAT_BRBE Enable Branch Record Buffer Extension +// CHECK-NEXT: FEAT_BTI Enable Branch Target Identification +// CHECK-NEXT: FEAT_CRC32 Enable Armv8.0-A CRC-32 checksum instructions +// CHECK-NEXT: FEAT_CSV2_2 Enable architectural speculation restriction +// CHECK-NEXT: FEAT_DIT Enable Armv8.4-A Data Independent Timing instructions +// CHECK-NEXT: FEAT_DPB Enable Armv8.2-A data Cache Clean to Point of Persistence +// CHECK-NEXT: FEAT_DPB2 Enable Armv8.5-A Cache Clean to Point of Deep Persistence +// CHECK-NEXT: FEAT_DotProd Enable dot product support +// CHECK-NEXT: FEAT_ECV Enable enhanced counter virtualization extension +// CHECK-NEXT: FEAT_ETE Enable Embedded Trace Extension +// CHECK-NEXT: FEAT_FCMA Enable Armv8.3-A Floating-point complex number support +// CHECK-NEXT: FEAT_FGT Enable fine grained virtualization traps extension +// CHECK-NEXT: FEAT_FHM Enable FP16 FML instructions +// CHECK-NEXT: FEAT_FP Enable Armv8.0-A Floating Point Extensions +// CHECK-NEXT: FEAT_FP16 Enable half-precision floating-point data processing +// CHECK-NEXT: FEAT_FPAC Enable Armv8.3-A Pointer Authentication Faulting enhancement +// CHECK-NEXT: FEAT_FRINTTS Enable FRInt[32|64][Z|X] instructions that round a floating-point number to an integer (in FP format) forcing it to fit into a 32- or 64-bit int +// CHECK-NEXT: FEAT_FlagM Enable Armv8.4-A Flag Manipulation instructions +// CHECK-NEXT: FEAT_FlagM2 Enable alternative NZCV format for floating point comparisons +// CHECK-NEXT: FEAT_HBC Enable Armv8.8-A Hinted Conditional Branches Extension +// CHECK-NEXT: FEAT_HCX Enable Armv8.7-A HCRX_EL2 system register +// CHECK-NEXT: FEAT_I8MM Enable Matrix Multiply Int8 Extension +// CHECK-NEXT: FEAT_JSCVT Enable Armv8.3-A JavaScript FP conversion instructions +// CHECK-NEXT: FEAT_LOR Enable Armv8.1-A Limited Ordering Regions extension +// CHECK-NEXT: FEAT_LRCPC Enable support for RCPC extension +// CHECK-NEXT: FEAT_LRCPC2 Enable Armv8.4-A RCPC instructions with Immediate Offsets +// CHECK-NEXT: FEAT_LRCPC3 Enable Armv8.9-A RCPC instructions for A64 and Advanced SIMD and floating-point instruction set +// CHECK-NEXT: FEAT_LS64, FEAT_LS64_V, FEAT_LS64_ACCDATA Enable Armv8.7-A LD64B/ST64B Accelerator Extension +// CHECK-NEXT: FEAT_LSE Enable Armv8.1-A Large System Extension (LSE) atomic instructions +// CHECK-NEXT: FEAT_LSE2 Enable Armv8.4-A Large System Extension 2 (LSE2) atomicity rules +// CHECK-NEXT: FEAT_MPAM Enable Armv8.4-A Memory system Partitioning and Monitoring extension +// CHECK-NEXT: FEAT_NMI, FEAT_GICv3_NMI Enable Armv8.8-A Non-maskable Interrupts +// CHECK-NEXT: FEAT_NV, FEAT_NV2 Enable Armv8.4-A Nested Virtualization Enchancement +// CHECK-NEXT: FEAT_PAN Enable Armv8.1-A Privileged Access-Never extension +// CHECK-NEXT: FEAT_PAN2 Enable Armv8.2-A PAN s1e1R and s1e1W Variants +// CHECK-NEXT: FEAT_PAuth Enable Armv8.3-A Pointer Authentication extension +// CHECK-NEXT: FEAT_PMUv3 Enable Armv8.0-A PMUv3 Performance Monitors extension +// CHECK-NEXT: FEAT_RAS, FEAT_RASv1p1 Enable Armv8.0-A Reliability, Availability and Serviceability Extensions +// CHECK-NEXT: FEAT_RDM Enable Armv8.1-A Rounding Double Multiply Add/Subtract instructions +// CHECK-NEXT: FEAT_RME Enable Realm Management Extension +// CHECK-NEXT: FEAT_SB Enable Armv8.5-A Speculation Barrier +// CHECK-NEXT: FEAT_SEL2 Enable Armv8.4-A Secure Exception Level 2 extension +// CHECK-NEXT: FEAT_SHA1, FEAT_SHA256 Enable SHA1 and SHA256 support +// CHECK-NEXT: FEAT_SHA3, FEAT_SHA512 Enable SHA512 and SHA3 support +// CHECK-NEXT: FEAT_SM4, FEAT_SM3 Enable SM3 and SM4 support +// CHECK-NEXT: FEAT_SPE Enable Statistical Profiling extension +// CHECK-NEXT: FEAT_SPECRES Enable Armv8.5-A execution and data prediction invalidation instructions +// CHECK-NEXT: FEAT_SPEv1p2 Enable extra register in the Statistical Profiling Extension +// CHECK-NEXT: FEAT_SVE Enable Scalable Vector Extension (SVE) instructions +// CHECK-NEXT: FEAT_SVE2 Enable Scalable Vector Extension 2 (SVE2) instructions +// CHECK-NEXT: FEAT_SVE_AES, FEAT_SVE_PMULL128 Enable SVE AES and quadword SVE polynomial multiply instructions +// CHECK-NEXT: FEAT_SVE_BitPerm Enable bit permutation SVE2 instructions +// CHECK-NEXT: FEAT_SVE_SHA3 Enable SVE SHA3 instructions +// CHECK-NEXT: FEAT_SVE_SM4 Enable SVE SM4 instructions +// CHECK-NEXT: FEAT_TLBIOS, FEAT_TLBIRANGE Enable Armv8.4-A TLB Range and Maintenance instructions +// CHECK-NEXT: FEAT_TRBE Enable Trace Buffer Extension +// CHECK-NEXT: FEAT_TRF Enable Armv8.4-A Trace extension +// CHECK-NEXT: FEAT_UAO Enable Armv8.2-A UAO PState +// CHECK-NEXT: FEAT_VHE Enable Armv8.1-A Virtual Host extension +// CHECK-NEXT: FEAT_WFxT Enable Armv8.7-A WFET and WFIT instruction +// CHECK-NEXT: FEAT_XS Enable Armv8.7-A limited-TLB-maintenance instruction diff --git a/clang/test/Misc/target-invalid-cpu-note/aarch64.c b/clang/test/Misc/target-invalid-cpu-note/aarch64.c index 3a6cb9d4445eb..0dbd9a958fb43 100644 --- a/clang/test/Misc/target-invalid-cpu-note/aarch64.c +++ b/clang/test/Misc/target-invalid-cpu-note/aarch64.c @@ -85,6 +85,7 @@ // CHECK-SAME: {{^}}, gb10 // CHECK-SAME: {{^}}, generic // CHECK-SAME: {{^}}, grace +// CHECK-SAME: {{^}}, hip12 // CHECK-SAME: {{^}}, kryo // CHECK-SAME: {{^}}, neoverse-512tvb // CHECK-SAME: {{^}}, neoverse-e1 diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index 7a7f40da17de6..0c1499069ec85 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -680,6 +680,15 @@ def TuneTSV110 : SubtargetFeature<"tsv110", "ARMProcFamily", "TSV110", FeatureStorePairSuppress, FeaturePostRAScheduler]>; +def TuneHIP12 : SubtargetFeature<"hip12", "ARMProcFamily", "HIP12", + "HiSilicon HIP12 processors", [ + FeatureCmpBccFusion, + FeatureFuseAES, + FeatureAddrLSLSlow14, + FeatureALULSLFast, + FeatureStorePairSuppress, + FeaturePostRAScheduler]>; + def TuneAmpere1 : SubtargetFeature<"ampere1", "ARMProcFamily", "Ampere1", "Ampere Computing Ampere-1 processors", [ FeaturePostRAScheduler, @@ -1201,6 +1210,20 @@ def ProcessorFeatures { FeatureFullFP16, FeatureFP16FML, FeatureDotProd, FeatureJS, FeatureComplxNum, FeatureCRC, FeatureLSE, FeatureRAS, FeatureRDM]; + list<SubtargetFeature> HIP12 = [HasV8_7aOps, FeatureSVE, FeatureSVE2, + FeatureSVEBitPerm, FeatureSVEAES, + FeatureSVESM4, FeatureSVESHA3, + FeatureFullFP16, FeaturePerfMon, + FeatureETE, FeatureTRBE, FeatureSPE, + FeatureSPE_EEF, FeatureNMI, + FeatureHBC, FeatureRCPC3, FeatureBF16, + FeatureComplxNum, FeatureCRC, + FeatureDotProd, FeatureFPARMv8, + FeatureMatMulInt8, FeatureJS, + FeatureLSE, FeatureNEON, FeaturePAuth, + FeatureRAS, FeatureRCPC, FeatureRDM, + FeatureFPAC, FeatureLS64, FeatureRME, + FeatureBRBE]; list<SubtargetFeature> Ampere1 = [HasV8_6aOps, FeatureNEON, FeaturePerfMon, FeatureSSBS, FeatureRandGen, FeatureSB, FeatureSHA2, FeatureSHA3, FeatureAES, @@ -1385,9 +1408,13 @@ def : ProcessorModel<"thunderx2t99", ThunderX2T99Model, // Marvell ThunderX3T110 Processors. def : ProcessorModel<"thunderx3t110", ThunderX3T110Model, ProcessorFeatures.ThunderX3T110, [TuneThunderX3T110]>; + +// HiSilicon Processors. def : ProcessorModel<"tsv110", TSV110Model, ProcessorFeatures.TSV110, [TuneTSV110]>; - +// TODO: Support hip12 model. +def : ProcessorModel<"hip12", NeoverseV2Model, ProcessorFeatures.HIP12, + [TuneHIP12]>; // Apple CPUs diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index eea1e61d4da17..f4b0af0333f4e 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -304,6 +304,12 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) { PrefFunctionAlignment = Align(16); PrefLoopAlignment = Align(4); break; + case HIP12: + PrefFunctionAlignment = Align(16); + PrefLoopAlignment = Align(4); + VScaleForTuning = 2; + DefaultSVETFOpts = TailFoldingOpts::Simple; + break; case ThunderX3T110: PrefFunctionAlignment = Align(16); PrefLoopAlignment = Align(4); diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp index 34f4b17a3855e..b43b30de96c1e 100644 --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -301,6 +301,7 @@ getHostCPUNameForARMFromComponents(StringRef Implementer, StringRef Hardware, // contents are specified in the various processor manuals. return StringSwitch<const char *>(Part) .Case("0xd01", "tsv110") + .Case("0xd06", "hip12") .Default("generic"); if (Implementer == "0x51") // Qualcomm Technologies, Inc. diff --git a/llvm/test/CodeGen/AArch64/cpus.ll b/llvm/test/CodeGen/AArch64/cpus.ll index f76a2c462c321..8bc758a6a432b 100644 --- a/llvm/test/CodeGen/AArch64/cpus.ll +++ b/llvm/test/CodeGen/AArch64/cpus.ll @@ -36,6 +36,7 @@ ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx2t99 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=thunderx3t110 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=tsv110 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=hip12 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=apple-latest 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=a64fx 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=fujitsu-monaka 2>&1 | FileCheck %s diff --git a/llvm/unittests/Target/AArch64/AArch64CacheLineSizeTest.cpp b/llvm/unittests/Target/AArch64/AArch64CacheLineSizeTest.cpp index dc227dd06b321..6fca5b231d84e 100644 --- a/llvm/unittests/Target/AArch64/AArch64CacheLineSizeTest.cpp +++ b/llvm/unittests/Target/AArch64/AArch64CacheLineSizeTest.cpp @@ -56,6 +56,7 @@ TEST_F(AArch64CacheLineSizeTest, IsCorrect) { EXPECT_EQ(getCacheLineSizeForCPU("thunderx2t99"), 64u); EXPECT_EQ(getCacheLineSizeForCPU("thunderx3t110"), 64u); EXPECT_EQ(getCacheLineSizeForCPU("tsv110"), 64u); + EXPECT_EQ(getCacheLineSizeForCPU("hip12"), 64u); } } // namespace diff --git a/llvm/unittests/TargetParser/Host.cpp b/llvm/unittests/TargetParser/Host.cpp index 2d2444152906d..4a63293960c02 100644 --- a/llvm/unittests/TargetParser/Host.cpp +++ b/llvm/unittests/TargetParser/Host.cpp @@ -330,6 +330,10 @@ CPU part : 0x0a1 "CPU part : 0xd01"), "tsv110"); + EXPECT_EQ(sys::detail::getHostCPUNameForARM("CPU implementer : 0x48\n" + "CPU part : 0xd06"), + "hip12"); + // Verify A64FX. const std::string A64FXProcCpuInfo = R"( processor : 0 diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 6377b197d911e..b60772b24cb2c 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1170,6 +1170,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64CPUTestParams("thunderxt83", "armv8-a"), AArch64CPUTestParams("thunderxt88", "armv8-a"), AArch64CPUTestParams("tsv110", "armv8.2-a"), + AArch64CPUTestParams("hip12", "armv8.7-a"), AArch64CPUTestParams("a64fx", "armv8.2-a"), AArch64CPUTestParams("fujitsu-monaka", "armv9.3-a"), AArch64CPUTestParams("carmel", "armv8.2-a"), @@ -1271,7 +1272,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64CPUAliasTestParams::PrintToStringParamName); // Note: number of CPUs includes aliases. -static constexpr unsigned NumAArch64CPUArchs = 98; +static constexpr unsigned NumAArch64CPUArchs = 99; TEST(TargetParserTest, testAArch64CPUArchList) { SmallVector<StringRef, NumAArch64CPUArchs> List; `````````` </details> https://github.com/llvm/llvm-project/pull/203446 _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
