https://github.com/iamvickynguyen updated https://github.com/llvm/llvm-project/pull/202005
>From d39dd4cbb715fef226f5105cffe8105187042679 Mon Sep 17 00:00:00 2001 From: Vicky Nguyen <[email protected]> Date: Fri, 5 Jun 2026 21:43:44 -0700 Subject: [PATCH] [CIR][AArch64] Upstream addition and polynomial-addition NEON builtins --- .../lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp | 23 +- clang/test/CodeGen/AArch64/neon-intrinsics.c | 222 +--------------- clang/test/CodeGen/AArch64/neon/add.c | 105 ++++++++ clang/test/CodeGen/AArch64/neon/intrinsics.c | 247 ++++++++++++++++++ clang/test/CodeGen/AArch64/poly-add.c | 86 ------ 5 files changed, 374 insertions(+), 309 deletions(-) create mode 100644 clang/test/CodeGen/AArch64/neon/add.c delete mode 100644 clang/test/CodeGen/AArch64/poly-add.c diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp index 4111df26d241d..56593ecfcd055 100644 --- a/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinAArch64.cpp @@ -672,8 +672,20 @@ static mlir::Value emitCommonNeonBuiltinExpr( case NEON::BI__builtin_neon_vpaddq_v: case NEON::BI__builtin_neon_vabs_v: case NEON::BI__builtin_neon_vabsq_v: + cgf.cgm.errorNYI(expr->getSourceRange(), + std::string("unimplemented AArch64 builtin call: ") + + ctx.BuiltinInfo.getName(builtinID)); + return mlir::Value{}; case NEON::BI__builtin_neon_vadd_v: - case NEON::BI__builtin_neon_vaddq_v: + case NEON::BI__builtin_neon_vaddq_v: { + unsigned numBytes = (builtinID == NEON::BI__builtin_neon_vaddq_v) ? 16 : 8; + cir::VectorType byteTy = + cir::VectorType::get(cgf.getBuilder().getUInt8Ty(), numBytes); + ops[0] = cgf.getBuilder().createBitcast(ops[0], byteTy); + ops[1] = cgf.getBuilder().createBitcast(ops[1], byteTy); + mlir::Value result = cgf.getBuilder().createXor(loc, ops[0], ops[1]); + return cgf.getBuilder().createBitcast(result, ty); + } case NEON::BI__builtin_neon_vaddhn_v: case NEON::BI__builtin_neon_vcale_v: case NEON::BI__builtin_neon_vcaleq_v: @@ -2352,7 +2364,13 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, case NEON::BI__builtin_neon_vabsh_f16: { return cir::FAbsOp::create(builder, loc, ops); } - case NEON::BI__builtin_neon_vaddq_p128: + case NEON::BI__builtin_neon_vaddq_p128: { + cir::VectorType byteTy = cir::VectorType::get(builder.getUInt8Ty(), 16); + ops[0] = builder.createBitcast(ops[0], byteTy); + ops[1] = builder.createBitcast(ops[1], byteTy); + mlir::Value result = builder.createXor(loc, ops[0], ops[1]); + return builder.createBitcast(result, convertType(expr->getType())); + } case NEON::BI__builtin_neon_vldrq_p128: case NEON::BI__builtin_neon_vstrq_p128: case NEON::BI__builtin_neon_vcvts_f32_u32: @@ -2528,6 +2546,7 @@ CIRGenFunction::emitAArch64BuiltinExpr(unsigned builtinID, const CallExpr *expr, convertType(expr->getType()), ops); case NEON::BI__builtin_neon_vaddd_s64: case NEON::BI__builtin_neon_vaddd_u64: + return builder.createAdd(loc, ops[0], ops[1]); case NEON::BI__builtin_neon_vsubd_s64: case NEON::BI__builtin_neon_vsubd_u64: case NEON::BI__builtin_neon_vqdmlalh_s16: diff --git a/clang/test/CodeGen/AArch64/neon-intrinsics.c b/clang/test/CodeGen/AArch64/neon-intrinsics.c index 5865c4cf61b50..d0b6bb89c40e2 100644 --- a/clang/test/CodeGen/AArch64/neon-intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon-intrinsics.c @@ -5,198 +5,8 @@ #include <arm_neon.h> -// CHECK-LABEL: define dso_local <8 x i8> @test_vadd_s8( -// CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) #[[ATTR0:[0-9]+]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[V1]], [[V2]] -// CHECK-NEXT: ret <8 x i8> [[ADD_I]] -// -int8x8_t test_vadd_s8(int8x8_t v1, int8x8_t v2) { - return vadd_s8(v1, v2); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vadd_s16( -// CHECK-SAME: <4 x i16> noundef [[V1:%.*]], <4 x i16> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[V1]], [[V2]] -// CHECK-NEXT: ret <4 x i16> [[ADD_I]] -// -int16x4_t test_vadd_s16(int16x4_t v1, int16x4_t v2) { - return vadd_s16(v1, v2); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vadd_s32( -// CHECK-SAME: <2 x i32> noundef [[V1:%.*]], <2 x i32> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[V1]], [[V2]] -// CHECK-NEXT: ret <2 x i32> [[ADD_I]] -// -int32x2_t test_vadd_s32(int32x2_t v1, int32x2_t v2) { - return vadd_s32(v1, v2); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vadd_s64( -// CHECK-SAME: <1 x i64> noundef [[V1:%.*]], <1 x i64> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = add <1 x i64> [[V1]], [[V2]] -// CHECK-NEXT: ret <1 x i64> [[ADD_I]] -// -int64x1_t test_vadd_s64(int64x1_t v1, int64x1_t v2) { - return vadd_s64(v1, v2); -} - -// CHECK-LABEL: define dso_local <2 x float> @test_vadd_f32( -// CHECK-SAME: <2 x float> noundef [[V1:%.*]], <2 x float> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = fadd <2 x float> [[V1]], [[V2]] -// CHECK-NEXT: ret <2 x float> [[ADD_I]] -// -float32x2_t test_vadd_f32(float32x2_t v1, float32x2_t v2) { - return vadd_f32(v1, v2); -} - -// CHECK-LABEL: define dso_local <8 x i8> @test_vadd_u8( -// CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i8> [[V1]], [[V2]] -// CHECK-NEXT: ret <8 x i8> [[ADD_I]] -// -uint8x8_t test_vadd_u8(uint8x8_t v1, uint8x8_t v2) { - return vadd_u8(v1, v2); -} - -// CHECK-LABEL: define dso_local <4 x i16> @test_vadd_u16( -// CHECK-SAME: <4 x i16> noundef [[V1:%.*]], <4 x i16> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i16> [[V1]], [[V2]] -// CHECK-NEXT: ret <4 x i16> [[ADD_I]] -// -uint16x4_t test_vadd_u16(uint16x4_t v1, uint16x4_t v2) { - return vadd_u16(v1, v2); -} - -// CHECK-LABEL: define dso_local <2 x i32> @test_vadd_u32( -// CHECK-SAME: <2 x i32> noundef [[V1:%.*]], <2 x i32> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i32> [[V1]], [[V2]] -// CHECK-NEXT: ret <2 x i32> [[ADD_I]] -// -uint32x2_t test_vadd_u32(uint32x2_t v1, uint32x2_t v2) { - return vadd_u32(v1, v2); -} - -// CHECK-LABEL: define dso_local <1 x i64> @test_vadd_u64( -// CHECK-SAME: <1 x i64> noundef [[V1:%.*]], <1 x i64> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = add <1 x i64> [[V1]], [[V2]] -// CHECK-NEXT: ret <1 x i64> [[ADD_I]] -// -uint64x1_t test_vadd_u64(uint64x1_t v1, uint64x1_t v2) { - return vadd_u64(v1, v2); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vaddq_s8( -// CHECK-SAME: <16 x i8> noundef [[V1:%.*]], <16 x i8> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = add <16 x i8> [[V1]], [[V2]] -// CHECK-NEXT: ret <16 x i8> [[ADD_I]] -// -int8x16_t test_vaddq_s8(int8x16_t v1, int8x16_t v2) { - return vaddq_s8(v1, v2); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vaddq_s16( -// CHECK-SAME: <8 x i16> noundef [[V1:%.*]], <8 x i16> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[V1]], [[V2]] -// CHECK-NEXT: ret <8 x i16> [[ADD_I]] -// -int16x8_t test_vaddq_s16(int16x8_t v1, int16x8_t v2) { - return vaddq_s16(v1, v2); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vaddq_s32( -// CHECK-SAME: <4 x i32> noundef [[V1:%.*]], <4 x i32> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[V1]], [[V2]] -// CHECK-NEXT: ret <4 x i32> [[ADD_I]] -// -int32x4_t test_vaddq_s32(int32x4_t v1, int32x4_t v2) { - return vaddq_s32(v1, v2); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vaddq_s64( -// CHECK-SAME: <2 x i64> noundef [[V1:%.*]], <2 x i64> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[V1]], [[V2]] -// CHECK-NEXT: ret <2 x i64> [[ADD_I]] -// -int64x2_t test_vaddq_s64(int64x2_t v1, int64x2_t v2) { - return vaddq_s64(v1, v2); -} - -// CHECK-LABEL: define dso_local <4 x float> @test_vaddq_f32( -// CHECK-SAME: <4 x float> noundef [[V1:%.*]], <4 x float> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = fadd <4 x float> [[V1]], [[V2]] -// CHECK-NEXT: ret <4 x float> [[ADD_I]] -// -float32x4_t test_vaddq_f32(float32x4_t v1, float32x4_t v2) { - return vaddq_f32(v1, v2); -} - -// CHECK-LABEL: define dso_local <2 x double> @test_vaddq_f64( -// CHECK-SAME: <2 x double> noundef [[V1:%.*]], <2 x double> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = fadd <2 x double> [[V1]], [[V2]] -// CHECK-NEXT: ret <2 x double> [[ADD_I]] -// -float64x2_t test_vaddq_f64(float64x2_t v1, float64x2_t v2) { - return vaddq_f64(v1, v2); -} - -// CHECK-LABEL: define dso_local <16 x i8> @test_vaddq_u8( -// CHECK-SAME: <16 x i8> noundef [[V1:%.*]], <16 x i8> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = add <16 x i8> [[V1]], [[V2]] -// CHECK-NEXT: ret <16 x i8> [[ADD_I]] -// -uint8x16_t test_vaddq_u8(uint8x16_t v1, uint8x16_t v2) { - return vaddq_u8(v1, v2); -} - -// CHECK-LABEL: define dso_local <8 x i16> @test_vaddq_u16( -// CHECK-SAME: <8 x i16> noundef [[V1:%.*]], <8 x i16> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = add <8 x i16> [[V1]], [[V2]] -// CHECK-NEXT: ret <8 x i16> [[ADD_I]] -// -uint16x8_t test_vaddq_u16(uint16x8_t v1, uint16x8_t v2) { - return vaddq_u16(v1, v2); -} - -// CHECK-LABEL: define dso_local <4 x i32> @test_vaddq_u32( -// CHECK-SAME: <4 x i32> noundef [[V1:%.*]], <4 x i32> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = add <4 x i32> [[V1]], [[V2]] -// CHECK-NEXT: ret <4 x i32> [[ADD_I]] -// -uint32x4_t test_vaddq_u32(uint32x4_t v1, uint32x4_t v2) { - return vaddq_u32(v1, v2); -} - -// CHECK-LABEL: define dso_local <2 x i64> @test_vaddq_u64( -// CHECK-SAME: <2 x i64> noundef [[V1:%.*]], <2 x i64> noundef [[V2:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = add <2 x i64> [[V1]], [[V2]] -// CHECK-NEXT: ret <2 x i64> [[ADD_I]] -// -uint64x2_t test_vaddq_u64(uint64x2_t v1, uint64x2_t v2) { - return vaddq_u64(v1, v2); -} - // CHECK-LABEL: define dso_local <8 x i8> @test_vsub_s8( -// CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) #[[ATTR0]] { +// CHECK-SAME: <8 x i8> noundef [[V1:%.*]], <8 x i8> noundef [[V2:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-NEXT: [[ENTRY:.*:]] // CHECK-NEXT: [[SUB_I:%.*]] = sub <8 x i8> [[V1]], [[V2]] // CHECK-NEXT: ret <8 x i8> [[SUB_I]] @@ -8240,26 +8050,6 @@ int64x2_t test_vqdmlsl_high_s32(int64x2_t a, int32x4_t b, int32x4_t c) { return vqdmlsl_high_s32(a, b, c); } -// CHECK-LABEL: define dso_local i64 @test_vaddd_s64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VADDD_I:%.*]] = add i64 [[A]], [[B]] -// CHECK-NEXT: ret i64 [[VADDD_I]] -// -int64_t test_vaddd_s64(int64_t a, int64_t b) { - return vaddd_s64(a, b); -} - -// CHECK-LABEL: define dso_local i64 @test_vaddd_u64( -// CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[VADDD_I:%.*]] = add i64 [[A]], [[B]] -// CHECK-NEXT: ret i64 [[VADDD_I]] -// -uint64_t test_vaddd_u64(uint64_t a, uint64_t b) { - return vaddd_u64(a, b); -} - // CHECK-LABEL: define dso_local i64 @test_vsubd_s64( // CHECK-SAME: i64 noundef [[A:%.*]], i64 noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] @@ -18496,16 +18286,6 @@ uint64_t test_vpaddd_u64(uint64x2_t a) { return vpaddd_u64(a); } -// CHECK-LABEL: define dso_local <1 x double> @test_vadd_f64( -// CHECK-SAME: <1 x double> noundef [[A:%.*]], <1 x double> noundef [[B:%.*]]) #[[ATTR0]] { -// CHECK-NEXT: [[ENTRY:.*:]] -// CHECK-NEXT: [[ADD_I:%.*]] = fadd <1 x double> [[A]], [[B]] -// CHECK-NEXT: ret <1 x double> [[ADD_I]] -// -float64x1_t test_vadd_f64(float64x1_t a, float64x1_t b) { - return vadd_f64(a, b); -} - // CHECK-LABEL: define dso_local <1 x double> @test_vmul_f64( // CHECK-SAME: <1 x double> noundef [[A:%.*]], <1 x double> noundef [[B:%.*]]) #[[ATTR0]] { // CHECK-NEXT: [[ENTRY:.*:]] diff --git a/clang/test/CodeGen/AArch64/neon/add.c b/clang/test/CodeGen/AArch64/neon/add.c new file mode 100644 index 0000000000000..916f4af59363e --- /dev/null +++ b/clang/test/CodeGen/AArch64/neon/add.c @@ -0,0 +1,105 @@ +// REQUIRES: aarch64-registered-target || arm-registered-target + +// RUN: %clang_cc1_cg_arm64_neon -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefix=LLVM +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-llvm %s -disable-O0-optnone | opt -S -passes=mem2reg,sroa | FileCheck %s --check-prefix=LLVM %} +// RUN: %if cir-enabled %{%clang_cc1_cg_arm64_neon -fclangir -emit-cir %s -disable-O0-optnone | FileCheck %s --check-prefix=CIR %} + +#include <arm_neon.h> + +//===----------------------------------------------------------------------===// +// 2.2.2.1.2. Polynomial addition +// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#polynomial-addition +//===----------------------------------------------------------------------===// + +// LLVM-LABEL: @test_vadd_p8( +// CIR-LABEL: @vadd_p8( +poly8x8_t test_vadd_p8(poly8x8_t a, poly8x8_t b) { + // CIR: cir.xor {{.*}} : !cir.vector<8 x !u8i> + + // LLVM-SAME: <8 x i8> {{.*}} [[A:%.*]], <8 x i8> {{.*}} [[B:%.*]]) + // LLVM: [[TMP0:%.*]] = xor <8 x i8> [[A]], [[B]] + // LLVM-NEXT: ret <8 x i8> [[TMP0]] + return vadd_p8(a, b); +} + +// LLVM-LABEL: @test_vadd_p16( +// CIR-LABEL: @vadd_p16( +poly16x4_t test_vadd_p16(poly16x4_t a, poly16x4_t b) { + // CIR: cir.xor {{.*}} : !cir.vector<8 x !u8i> + + // LLVM-SAME: <4 x i16> {{.*}} [[A:%.*]], <4 x i16> {{.*}} [[B:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <4 x i16> [[A]] to <8 x i8> + // LLVM-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B]] to <8 x i8> + // LLVM-NEXT: [[TMP2:%.*]] = xor <8 x i8> [[TMP0]], [[TMP1]] + // LLVM-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> + // LLVM-NEXT: ret <4 x i16> [[TMP3]] + return vadd_p16(a, b); +} + +// LLVM-LABEL: @test_vadd_p64( +// CIR-LABEL: @vadd_p64( +poly64x1_t test_vadd_p64(poly64x1_t a, poly64x1_t b) { + // CIR: cir.xor {{.*}} : !cir.vector<8 x !u8i> + + // LLVM-SAME: <1 x i64> {{.*}} [[A:%.*]], <1 x i64> {{.*}} [[B:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <1 x i64> [[A]] to <8 x i8> + // LLVM-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B]] to <8 x i8> + // LLVM-NEXT: [[TMP2:%.*]] = xor <8 x i8> [[TMP0]], [[TMP1]] + // LLVM-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64> + // LLVM-NEXT: ret <1 x i64> [[TMP3]] + return vadd_p64(a, b); +} + +// LLVM-LABEL: @test_vaddq_p8( +// CIR-LABEL: @vaddq_p8( +poly8x16_t test_vaddq_p8(poly8x16_t a, poly8x16_t b) { + // CIR: cir.xor {{.*}} : !cir.vector<16 x !u8i> + + // LLVM-SAME: <16 x i8> {{.*}} [[A:%.*]], <16 x i8> {{.*}} [[B:%.*]]) + // LLVM: [[TMP0:%.*]] = xor <16 x i8> [[A]], [[B]] + // LLVM-NEXT: ret <16 x i8> [[TMP0]] + return vaddq_p8(a, b); +} + +// LLVM-LABEL: @test_vaddq_p16( +// CIR-LABEL: @vaddq_p16( +poly16x8_t test_vaddq_p16(poly16x8_t a, poly16x8_t b) { + // CIR: cir.xor {{.*}} : !cir.vector<16 x !u8i> + + // LLVM-SAME: <8 x i16> {{.*}} [[A:%.*]], <8 x i16> {{.*}} [[B:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <8 x i16> [[A]] to <16 x i8> + // LLVM-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B]] to <16 x i8> + // LLVM-NEXT: [[TMP2:%.*]] = xor <16 x i8> [[TMP0]], [[TMP1]] + // LLVM-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16> + // LLVM-NEXT: ret <8 x i16> [[TMP3]] + return vaddq_p16(a, b); +} + +// LLVM-LABEL: @test_vaddq_p64( +// CIR-LABEL: @vaddq_p64( +poly64x2_t test_vaddq_p64(poly64x2_t a, poly64x2_t b) { + // CIR: cir.xor {{.*}} : !cir.vector<16 x !u8i> + + // LLVM-SAME: <2 x i64> {{.*}} [[A:%.*]], <2 x i64> {{.*}} [[B:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast <2 x i64> [[A]] to <16 x i8> + // LLVM-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B]] to <16 x i8> + // LLVM-NEXT: [[TMP2:%.*]] = xor <16 x i8> [[TMP0]], [[TMP1]] + // LLVM-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64> + // LLVM-NEXT: ret <2 x i64> [[TMP3]] + return vaddq_p64(a, b); +} + +// LLVM-LABEL: @test_vaddq_p128( +// CIR-LABEL: @vaddq_p128( +poly128_t test_vaddq_p128(poly128_t a, poly128_t b) { + // CIR: cir.xor {{.*}} : !cir.vector<16 x !u8i> + + // LLVM-SAME: i128 {{.*}} [[A:%.*]], i128 {{.*}} [[B:%.*]]) + // LLVM: [[TMP0:%.*]] = bitcast i128 [[A]] to <16 x i8> + // LLVM-NEXT: [[TMP1:%.*]] = bitcast i128 [[B]] to <16 x i8> + // LLVM-NEXT: [[TMP2:%.*]] = xor <16 x i8> [[TMP0]], [[TMP1]] + // LLVM-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to i128 + // LLVM-NEXT: ret i128 [[TMP3]] + return vaddq_p128(a, b); +} + diff --git a/clang/test/CodeGen/AArch64/neon/intrinsics.c b/clang/test/CodeGen/AArch64/neon/intrinsics.c index e72d38cbdb5a8..6b4a8c86181ce 100644 --- a/clang/test/CodeGen/AArch64/neon/intrinsics.c +++ b/clang/test/CodeGen/AArch64/neon/intrinsics.c @@ -6767,3 +6767,250 @@ float64_t test_vpmaxnmqd_f64(float64x2_t a) { // LLVM-NEXT: ret double [[VPMAXNMQD_F64_I]] return vpmaxnmqd_f64(a); } + +//===------------------------------------------------------===// +// 2.1.1.1.1 Addition +// https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#addition +//===------------------------------------------------------===// + +// LLVM-LABEL: @test_vadd_s8( +// CIR-LABEL: @vadd_s8( +int8x8_t test_vadd_s8(int8x8_t a, int8x8_t b) { +// CIR: cir.add + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = add <8 x i8> [[A]], [[B]] +// LLVM: ret <8 x i8> [[ADD_I]] + return vadd_s8(a, b); +} + +// LLVM-LABEL: @test_vadd_s16( +// CIR-LABEL: @vadd_s16( +int16x4_t test_vadd_s16(int16x4_t a, int16x4_t b) { +// CIR: cir.add + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = add <4 x i16> [[A]], [[B]] +// LLVM: ret <4 x i16> [[ADD_I]] + return vadd_s16(a, b); +} + +// LLVM-LABEL: @test_vadd_s32( +// CIR-LABEL: @vadd_s32( +int32x2_t test_vadd_s32(int32x2_t a, int32x2_t b) { +// CIR: cir.add + +// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = add <2 x i32> [[A]], [[B]] +// LLVM: ret <2 x i32> [[ADD_I]] + return vadd_s32(a, b); +} + +// LLVM-LABEL: @test_vadd_s64( +// CIR-LABEL: @vadd_s64( +int64x1_t test_vadd_s64(int64x1_t a, int64x1_t b) { +// CIR: cir.add + +// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = add <1 x i64> [[A]], [[B]] +// LLVM: ret <1 x i64> [[ADD_I]] + return vadd_s64(a, b); +} + +// LLVM-LABEL: @test_vadd_f32( +// CIR-LABEL: @vadd_f32( +float32x2_t test_vadd_f32(float32x2_t a, float32x2_t b) { +// CIR: cir.fadd + +// LLVM-SAME: <2 x float> {{.*}}[[A:%.*]], <2 x float> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = fadd <2 x float> [[A]], [[B]] +// LLVM: ret <2 x float> [[ADD_I]] + return vadd_f32(a, b); +} + +// LLVM-LABEL: @test_vadd_u8( +// CIR-LABEL: @vadd_u8( +uint8x8_t test_vadd_u8(uint8x8_t a, uint8x8_t b) { +// CIR: cir.add + +// LLVM-SAME: <8 x i8> {{.*}}[[A:%.*]], <8 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = add <8 x i8> [[A]], [[B]] +// LLVM: ret <8 x i8> [[ADD_I]] + return vadd_u8(a, b); +} + +// LLVM-LABEL: @test_vadd_u16( +// CIR-LABEL: @vadd_u16( +uint16x4_t test_vadd_u16(uint16x4_t a, uint16x4_t b) { +// CIR: cir.add + +// LLVM-SAME: <4 x i16> {{.*}}[[A:%.*]], <4 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = add <4 x i16> [[A]], [[B]] +// LLVM: ret <4 x i16> [[ADD_I]] + return vadd_u16(a, b); +} + +// LLVM-LABEL: @test_vadd_u32( +// CIR-LABEL: @vadd_u32( +uint32x2_t test_vadd_u32(uint32x2_t a, uint32x2_t b) { +// CIR: cir.add + +// LLVM-SAME: <2 x i32> {{.*}}[[A:%.*]], <2 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = add <2 x i32> [[A]], [[B]] +// LLVM: ret <2 x i32> [[ADD_I]] + return vadd_u32(a, b); +} + +// LLVM-LABEL: @test_vadd_u64( +// CIR-LABEL: @vadd_u64( +uint64x1_t test_vadd_u64(uint64x1_t a, uint64x1_t b) { +// CIR: cir.add + +// LLVM-SAME: <1 x i64> {{.*}}[[A:%.*]], <1 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = add <1 x i64> [[A]], [[B]] +// LLVM: ret <1 x i64> [[ADD_I]] + return vadd_u64(a, b); +} + +// LLVM-LABEL: @test_vaddq_s8( +// CIR-LABEL: @vaddq_s8( +int8x16_t test_vaddq_s8(int8x16_t a, int8x16_t b) { +// CIR: cir.add + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = add <16 x i8> [[A]], [[B]] +// LLVM: ret <16 x i8> [[ADD_I]] + return vaddq_s8(a, b); +} + +// LLVM-LABEL: @test_vaddq_s16( +// CIR-LABEL: @vaddq_s16( +int16x8_t test_vaddq_s16(int16x8_t a, int16x8_t b) { +// CIR: cir.add + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[B]] +// LLVM: ret <8 x i16> [[ADD_I]] + return vaddq_s16(a, b); +} + +// LLVM-LABEL: @test_vaddq_s32( +// CIR-LABEL: @vaddq_s32( +int32x4_t test_vaddq_s32(int32x4_t a, int32x4_t b) { +// CIR: cir.add + +// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[B]] +// LLVM: ret <4 x i32> [[ADD_I]] + return vaddq_s32(a, b); +} + +// LLVM-LABEL: @test_vaddq_s64( +// CIR-LABEL: @vaddq_s64( +int64x2_t test_vaddq_s64(int64x2_t a, int64x2_t b) { +// CIR: cir.add + +// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[B]] +// LLVM: ret <2 x i64> [[ADD_I]] + return vaddq_s64(a, b); +} + +// LLVM-LABEL: @test_vaddq_f32( +// CIR-LABEL: @vaddq_f32( +float32x4_t test_vaddq_f32(float32x4_t a, float32x4_t b) { +// CIR: cir.fadd + +// LLVM-SAME: <4 x float> {{.*}}[[A:%.*]], <4 x float> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = fadd <4 x float> [[A]], [[B]] +// LLVM: ret <4 x float> [[ADD_I]] + return vaddq_f32(a, b); +} + +// LLVM-LABEL: @test_vaddq_f64( +// CIR-LABEL: @vaddq_f64( +float64x2_t test_vaddq_f64(float64x2_t a, float64x2_t b) { +// CIR: cir.fadd + +// LLVM-SAME: <2 x double> {{.*}}[[A:%.*]], <2 x double> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = fadd <2 x double> [[A]], [[B]] +// LLVM: ret <2 x double> [[ADD_I]] + return vaddq_f64(a, b); +} + +// LLVM-LABEL: @test_vaddq_u8( +// CIR-LABEL: @vaddq_u8( +uint8x16_t test_vaddq_u8(uint8x16_t a, uint8x16_t b) { +// CIR: cir.add + +// LLVM-SAME: <16 x i8> {{.*}}[[A:%.*]], <16 x i8> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = add <16 x i8> [[A]], [[B]] +// LLVM: ret <16 x i8> [[ADD_I]] + return vaddq_u8(a, b); +} + +// LLVM-LABEL: @test_vaddq_u16( +// CIR-LABEL: @vaddq_u16( +uint16x8_t test_vaddq_u16(uint16x8_t a, uint16x8_t b) { +// CIR: cir.add + +// LLVM-SAME: <8 x i16> {{.*}}[[A:%.*]], <8 x i16> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = add <8 x i16> [[A]], [[B]] +// LLVM: ret <8 x i16> [[ADD_I]] + return vaddq_u16(a, b); +} + +// LLVM-LABEL: @test_vaddq_u32( +// CIR-LABEL: @vaddq_u32( +uint32x4_t test_vaddq_u32(uint32x4_t a, uint32x4_t b) { +// CIR: cir.add + +// LLVM-SAME: <4 x i32> {{.*}}[[A:%.*]], <4 x i32> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = add <4 x i32> [[A]], [[B]] +// LLVM: ret <4 x i32> [[ADD_I]] + return vaddq_u32(a, b); +} + +// LLVM-LABEL: @test_vaddq_u64( +// CIR-LABEL: @vaddq_u64( +uint64x2_t test_vaddq_u64(uint64x2_t a, uint64x2_t b) { +// CIR: cir.add + +// LLVM-SAME: <2 x i64> {{.*}}[[A:%.*]], <2 x i64> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = add <2 x i64> [[A]], [[B]] +// LLVM: ret <2 x i64> [[ADD_I]] + return vaddq_u64(a, b); +} + +// LLVM-LABEL: @test_vadd_f64( +// CIR-LABEL: @vadd_f64( +float64x1_t test_vadd_f64(float64x1_t a, float64x1_t b) { +// CIR: cir.fadd + +// LLVM-SAME: <1 x double> {{.*}}[[A:%.*]], <1 x double> {{.*}}[[B:%.*]]) +// LLVM: [[ADD_I:%.*]] = fadd <1 x double> [[A]], [[B]] +// LLVM: ret <1 x double> [[ADD_I]] + return vadd_f64(a, b); +} + +// LLVM-LABEL: @test_vaddd_s64( +// CIR-LABEL: @vaddd_s64( +int64_t test_vaddd_s64(int64_t a, int64_t b) { +// CIR: cir.add + +// LLVM-SAME: i64 {{.*}}[[A:%.*]], i64 {{.*}}[[B:%.*]]) +// LLVM: [[VADDD_I:%.*]] = add i64 [[A]], [[B]] +// LLVM: ret i64 [[VADDD_I]] + return vaddd_s64(a, b); +} + +// LLVM-LABEL: @test_vaddd_u64( +// CIR-LABEL: @vaddd_u64( +uint64_t test_vaddd_u64(uint64_t a, uint64_t b) { +// CIR: cir.add + +// LLVM-SAME: i64 {{.*}}[[A:%.*]], i64 {{.*}}[[B:%.*]]) +// LLVM: [[VADDD_I:%.*]] = add i64 [[A]], [[B]] +// LLVM: ret i64 [[VADDD_I]] + return vaddd_u64(a, b); +} diff --git a/clang/test/CodeGen/AArch64/poly-add.c b/clang/test/CodeGen/AArch64/poly-add.c deleted file mode 100644 index 069df72f87deb..0000000000000 --- a/clang/test/CodeGen/AArch64/poly-add.c +++ /dev/null @@ -1,86 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -triple aarch64-linux-gnu -target-feature +neon \ -// RUN: -disable-O0-optnone -emit-llvm -o - %s | opt -S -passes=mem2reg,sroa \ -// RUN: | FileCheck %s - -// REQUIRES: aarch64-registered-target - -#include <arm_neon.h> - -// CHECK-LABEL: @test_vadd_p8( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = xor <8 x i8> [[A:%.*]], [[B:%.*]] -// CHECK-NEXT: ret <8 x i8> [[TMP0]] -// -poly8x8_t test_vadd_p8(poly8x8_t a, poly8x8_t b) { - return vadd_p8 (a, b); -} - -// CHECK-LABEL: @test_vadd_p16( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i16> [[A:%.*]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i16> [[B:%.*]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = xor <8 x i8> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <4 x i16> -// CHECK-NEXT: ret <4 x i16> [[TMP3]] -// -poly16x4_t test_vadd_p16(poly16x4_t a, poly16x4_t b) { - return vadd_p16 (a, b); -} - -// CHECK-LABEL: @test_vadd_p64( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <1 x i64> [[A:%.*]] to <8 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <1 x i64> [[B:%.*]] to <8 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = xor <8 x i8> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <8 x i8> [[TMP2]] to <1 x i64> -// CHECK-NEXT: ret <1 x i64> [[TMP3]] -// -poly64x1_t test_vadd_p64(poly64x1_t a, poly64x1_t b) { - return vadd_p64(a, b); -} - -// CHECK-LABEL: @test_vaddq_p8( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = xor <16 x i8> [[A:%.*]], [[B:%.*]] -// CHECK-NEXT: ret <16 x i8> [[TMP0]] -// -poly8x16_t test_vaddq_p8(poly8x16_t a, poly8x16_t b){ - return vaddq_p8(a, b); -} - -// CHECK-LABEL: @test_vaddq_p16( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <8 x i16> [[A:%.*]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i16> [[B:%.*]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = xor <16 x i8> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <8 x i16> -// CHECK-NEXT: ret <8 x i16> [[TMP3]] -// -poly16x8_t test_vaddq_p16(poly16x8_t a, poly16x8_t b){ - return vaddq_p16(a, b); -} - -// CHECK-LABEL: @test_vaddq_p64( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[A:%.*]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[B:%.*]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = xor <16 x i8> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to <2 x i64> -// CHECK-NEXT: ret <2 x i64> [[TMP3]] -// -poly64x2_t test_vaddq_p64(poly64x2_t a, poly64x2_t b){ - return vaddq_p64(a, b); -} - -// CHECK-LABEL: @test_vaddq_p128( -// CHECK-NEXT: entry: -// CHECK-NEXT: [[TMP0:%.*]] = bitcast i128 [[A:%.*]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = bitcast i128 [[B:%.*]] to <16 x i8> -// CHECK-NEXT: [[TMP2:%.*]] = xor <16 x i8> [[TMP0]], [[TMP1]] -// CHECK-NEXT: [[TMP3:%.*]] = bitcast <16 x i8> [[TMP2]] to i128 -// CHECK-NEXT: ret i128 [[TMP3]] -// -poly128_t test_vaddq_p128 (poly128_t a, poly128_t b){ - return vaddq_p128(a, b); -} _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
