https://github.com/CarolineConcatto updated https://github.com/llvm/llvm-project/pull/203310
>From 84aabf7e253115b2b5107830c39f61a5db5d94aa Mon Sep 17 00:00:00 2001 From: CarolineConcatto <[email protected]> Date: Thu, 11 Jun 2026 12:56:31 +0000 Subject: [PATCH] [AArch64][SME] Split FP8 FTMOPA intrinsics Introduce separate FP8 FTMOPA intrinsics for ZA16 and ZA32: llvm.aarch64.sme.fp8.ftmopa.za16 llvm.aarch64.sme.fp8.ftmopa.za32 The FP8 FTMOPA forms need to model their FPMR dependency, so they should not share the same intrinsic definitions as the non-FP8 FTMOPA forms. Update the Clang SME builtin definitions and AArch64 instruction patterns to use the new intrinsics, and add AutoUpgrade support for the previous FP8-shaped llvm.aarch64.sme.ftmopa.* spellings so existing IR and bitcode continue to work. This was split out from #154144 because the intrinsic upgrade needs to be handled separately to avoid breaking existing bitcode. Fix test fpmpa --- clang/include/clang/Basic/arm_sme.td | 4 ++-- .../AArch64/sme2-intrinsics/acle_sme2_tmop.c | 8 +++---- llvm/include/llvm/IR/IntrinsicsAArch64.td | 14 ++++++++++++ llvm/lib/IR/AutoUpgrade.cpp | 15 +++++++++++++ .../lib/Target/AArch64/AArch64SMEInstrInfo.td | 4 ++-- .../upgrade-sme2-fp8-intrinsics-tmop.ll | 21 ++++++++++++++++++ .../upgrade-sme2-fp8-intrinsics-tmop.ll.bc | Bin 0 -> 2244 bytes .../CodeGen/AArch64/sme2-intrinsics-tmop.ll | 4 ++-- 8 files changed, 60 insertions(+), 10 deletions(-) create mode 100644 llvm/test/Bitcode/upgrade-sme2-fp8-intrinsics-tmop.ll create mode 100644 llvm/test/Bitcode/upgrade-sme2-fp8-intrinsics-tmop.ll.bc diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td index 032c588966032..5137e968bec55 100644 --- a/clang/include/clang/Basic/arm_sme.td +++ b/clang/include/clang/Basic/arm_sme.td @@ -915,11 +915,11 @@ let SMETargetGuard = "sme2,sme-tmop,sme-b16b16" in { } let SMETargetGuard = "sme2,sme-tmop,sme-f8f16" in { - def SVTMOPA_ZA16_FPM : Inst<"svtmopa_lane_za16[_{d}_{d}]", "vi2.dd[i>", "m", MergeNone, "aarch64_sme_ftmopa_za16", [IsStreaming, IsInOutZA], [ImmCheck<0, ImmCheck0_1>, ImmCheck<4, ImmCheck0_3>]>; + def SVTMOPA_ZA16_FPM : Inst<"svtmopa_lane_za16[_{d}_{d}]", "vi2.dd[i>", "m", MergeNone, "aarch64_sme_fp8_ftmopa_za16", [IsStreaming, IsInOutZA, IsOverloadNone], [ImmCheck<0, ImmCheck0_1>, ImmCheck<4, ImmCheck0_3>]>; } let SMETargetGuard = "sme2,sme-tmop,sme-f8f32" in { - def SVTMOPA_ZA32_FPM : Inst<"svtmopa_lane_za32[_{d}_{d}]", "vi2.dd[i>", "m", MergeNone, "aarch64_sme_ftmopa_za32", [IsStreaming, IsInOutZA], [ImmCheck<0, ImmCheck0_3>, ImmCheck<4, ImmCheck0_3>]>; + def SVTMOPA_ZA32_FPM : Inst<"svtmopa_lane_za32[_{d}_{d}]", "vi2.dd[i>", "m", MergeNone, "aarch64_sme_fp8_ftmopa_za32", [IsStreaming, IsInOutZA, IsOverloadNone], [ImmCheck<0, ImmCheck0_3>, ImmCheck<4, ImmCheck0_3>]>; } multiclass ZAReadz<string n_suffix, string vg_num, string t, string i_prefix, list<ImmCheck> ch> { diff --git a/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c b/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c index 55d0074663bc9..d68a465e092c6 100644 --- a/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c +++ b/clang/test/CodeGen/AArch64/sme2-intrinsics/acle_sme2_tmop.c @@ -172,13 +172,13 @@ void test_svtmopa_lane_za16_bf16_bf16(svbfloat16x2_t zn, svbfloat16_t zm, svuint // CHECK-LABEL: @test_svtmopa_lane_za16_mf8_mf8_fpm( // CHECK-NEXT: entry: // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR:%.*]]) -// CHECK-NEXT: tail call void @llvm.aarch64.sme.ftmopa.za16.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], <vscale x 16 x i8> [[ZK:%.*]], i32 3) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.ftmopa.za16(i32 1, <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], <vscale x 16 x i8> [[ZK:%.*]], i32 3) // CHECK-NEXT: ret void // // CPP-CHECK-LABEL: @_Z34test_svtmopa_lane_za16_mf8_mf8_fpm13svmfloat8x2_tu13__SVMfloat8_tu11__SVUint8_tm( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR:%.*]]) -// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.ftmopa.za16.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], <vscale x 16 x i8> [[ZK:%.*]], i32 3) +// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.ftmopa.za16(i32 1, <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], <vscale x 16 x i8> [[ZK:%.*]], i32 3) // CPP-CHECK-NEXT: ret void // void test_svtmopa_lane_za16_mf8_mf8_fpm(svmfloat8x2_t zn, svmfloat8_t zm, svuint8_t zk, fpm_t fpmr) __arm_streaming __arm_inout("za") { @@ -188,13 +188,13 @@ void test_svtmopa_lane_za16_mf8_mf8_fpm(svmfloat8x2_t zn, svmfloat8_t zm, svuint // CHECK-LABEL: @test_svtmopa_lane_za32_mf8_mf8_fpm( // CHECK-NEXT: entry: // CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR:%.*]]) -// CHECK-NEXT: tail call void @llvm.aarch64.sme.ftmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], <vscale x 16 x i8> [[ZK:%.*]], i32 3) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.ftmopa.za32(i32 1, <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], <vscale x 16 x i8> [[ZK:%.*]], i32 3) // CHECK-NEXT: ret void // // CPP-CHECK-LABEL: @_Z34test_svtmopa_lane_za32_mf8_mf8_fpm13svmfloat8x2_tu13__SVMfloat8_tu11__SVUint8_tm( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: tail call void @llvm.aarch64.set.fpmr(i64 [[FPMR:%.*]]) -// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.ftmopa.za32.nxv16i8(i32 1, <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], <vscale x 16 x i8> [[ZK:%.*]], i32 3) +// CPP-CHECK-NEXT: tail call void @llvm.aarch64.sme.fp8.ftmopa.za32(i32 1, <vscale x 16 x i8> [[ZN_COERCE0:%.*]], <vscale x 16 x i8> [[ZN_COERCE1:%.*]], <vscale x 16 x i8> [[ZM:%.*]], <vscale x 16 x i8> [[ZK:%.*]], i32 3) // CPP-CHECK-NEXT: ret void // void test_svtmopa_lane_za32_mf8_mf8_fpm(svmfloat8x2_t zn, svmfloat8_t zm, svuint8_t zk, fpm_t fpmr) __arm_streaming __arm_inout("za") { diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index ba0d7c02bf427..6cb96a635f87c 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -3142,6 +3142,20 @@ let TargetPrefix = "aarch64" in { def int_aarch64_sme_sutmopa_za32 : SME_OuterProduct_TMOP_Intrinsic; def int_aarch64_sme_ustmopa_za32 : SME_OuterProduct_TMOP_Intrinsic; + class SME_FP8_OuterProduct_TMOP_Intrinsic + : DefaultAttrsIntrinsic<[], + [llvm_i32_ty, + llvm_nxv16i8_ty, + llvm_nxv16i8_ty, + llvm_nxv16i8_ty, + llvm_nxv16i8_ty, + llvm_i32_ty], + [ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<5>>, + IntrInaccessibleMemOnly]>; + + def int_aarch64_sme_fp8_ftmopa_za16 : SME_FP8_OuterProduct_TMOP_Intrinsic; + def int_aarch64_sme_fp8_ftmopa_za32 : SME_FP8_OuterProduct_TMOP_Intrinsic; + // 16 and 32 bit multi-vector floating point 8 Quarter Tile Quarter Product foreach za = ["za16", "za32"] in { def int_aarch64_sme_fp8_fmop4a_ # za # "_1x1" : SME_OuterProduct_QuarterTile_Single_Single; diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp index 0770f0f0ff060..74b01200c064b 100644 --- a/llvm/lib/IR/AutoUpgrade.cpp +++ b/llvm/lib/IR/AutoUpgrade.cpp @@ -970,6 +970,21 @@ static bool upgradeArmOrAarch64IntrinsicFunction(bool IsArm, Function *F, } } else { // 'aarch64.*'. + if (Name.consume_front("sme.ftmopa.")) { + // The FP8 FTMOPA intrinsics were split out from the non-FP8 FTMOPA + // intrinsics to model their FPMR dependency. + Intrinsic::ID ID = + StringSwitch<Intrinsic::ID>(Name) + .Case("za16.nxv16i8", Intrinsic::aarch64_sme_fp8_ftmopa_za16) + .Case("za32.nxv16i8", Intrinsic::aarch64_sme_fp8_ftmopa_za32) + .Default(Intrinsic::not_intrinsic); + if (ID != Intrinsic::not_intrinsic) { + NewFn = Intrinsic::getOrInsertDeclaration(F->getParent(), ID); + return true; + } + return false; // No other 'aarch64.sme.ftmopa.*'. + } + if (Neon) { // 'aarch64.neon.*'. Intrinsic::ID ID = StringSwitch<Intrinsic::ID>(Name) diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td index 022fed6473486..5a7e4f22a7c0c 100644 --- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td @@ -224,11 +224,11 @@ let Predicates = [HasSME_TMOP, HasSMEB16B16] in { } let Predicates = [HasSME_TMOP, HasSMEF8F16] in { - defm FTMOPA_M2ZZZI_BtoH : sme_tmopa_16b<0b01001, ZZ_b_mul_r, ZPR8, nxv16i8, "ftmopa", int_aarch64_sme_ftmopa_za16, [FPMR, FPCR]>; + defm FTMOPA_M2ZZZI_BtoH : sme_tmopa_16b<0b01001, ZZ_b_mul_r, ZPR8, nxv16i8, "ftmopa", int_aarch64_sme_fp8_ftmopa_za16, [FPMR, FPCR]>; } let Predicates = [HasSME_TMOP, HasSMEF8F32] in { - defm FTMOPA_M2ZZZI_BtoS : sme_tmopa_32b<0b01000, ZZ_b_mul_r, ZPR8, nxv16i8, "ftmopa", int_aarch64_sme_ftmopa_za32, [FPMR, FPCR]>; + defm FTMOPA_M2ZZZI_BtoS : sme_tmopa_32b<0b01000, ZZ_b_mul_r, ZPR8, nxv16i8, "ftmopa", int_aarch64_sme_fp8_ftmopa_za32, [FPMR, FPCR]>; } let Predicates = [HasSME] in { diff --git a/llvm/test/Bitcode/upgrade-sme2-fp8-intrinsics-tmop.ll b/llvm/test/Bitcode/upgrade-sme2-fp8-intrinsics-tmop.ll new file mode 100644 index 0000000000000..524bb1e3cd4c7 --- /dev/null +++ b/llvm/test/Bitcode/upgrade-sme2-fp8-intrinsics-tmop.ll @@ -0,0 +1,21 @@ +; RUN: opt -S < %s | FileCheck %s +; RUN: llvm-dis < %s.bc | FileCheck %s + +target triple = "aarch64-linux" + +define void @ftmopa_za16_nxv16i8(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 { +; CHECK-LABEL: @ftmopa_za16_nxv16i8 +; CHECK: call void @llvm.aarch64.sme.fp8.ftmopa.za16(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk, i32 0) + call void @llvm.aarch64.sme.ftmopa.za16.nxv16i8(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk, i32 0) + ret void +} + +define void @ftmopa_za32_nxv16i8(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk) #0 { +; CHECK-LABEL: @ftmopa_za32_nxv16i +; CHECK: call void @llvm.aarch64.sme.fp8.ftmopa.za32(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk, i32 0) + call void @llvm.aarch64.sme.ftmopa.za32.nxv16i8(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk, i32 0) + ret void +} + + +attributes #0 = {nounwind "target-features" = "+sme2,+sme-tmop,+sme-f8f16,+sme-f8f32" } diff --git a/llvm/test/Bitcode/upgrade-sme2-fp8-intrinsics-tmop.ll.bc b/llvm/test/Bitcode/upgrade-sme2-fp8-intrinsics-tmop.ll.bc new file mode 100644 index 0000000000000000000000000000000000000000..46ab2bf08826cf8be5d30db39547a71e54326757 GIT binary patch literal 2244 zcma)7ZA=^46@6yF<0NLrY}jHiGqW>+ja)U*iTN61yTv#`j+)gvDL;tX3J(wmwuCjt zF(28kZ0s^@i&joWQ@2ee=vHkiwGyfLfmGDm3`<>hl+vh*P!=IO7?M;Zuz_76HBx&A zLe)Q2`!s&fbM@Yxd(S!dzD8GawWb)M0)$YTo-cp%(jR{LoqtTfRhlk8qp=hqPLI$t z4MNBAIFtu_%HW4b%5FH*`RB9-i}eSZnEs6dor%f+ep}dZHm~t}WwG*-n2zf(`wjff z;*OZ%hWF2nBl@Bv9|#>W_rrM63HQaY-o)L^>qzU0%B>AeqlS+)md2Rd((GwwKb&c3 z3PkiK%LsY%OO}|?bdIoe%(n#MTv=264Fg>tOpksL=gy3b<y)!|dY?szfS6AB@(sUh z96nNX5vCixa~}86BPY)+6f`!T)EQpWB+42_Oe|+Ut0+oQ*lGQ_&-XT*MCgJMAr98k z&)L0y!qCKZLppp=kOC7@EiVOh_|R>9&@2t2`(Eb3B$W#n9{hO_W*%heOyux2No^;o zhe=}DTevYvFHROJ8d4F799rJisgA#jeuefl+juyC*XccWN;k}^&(YFR4()j{rxCr5 z&Ot0H#>a=fbF4le9sh|RLNVgODXhK|3%T+B+xWXnIx!$<ukBr8PX6c{JE2SWEpqQ~ zr+-@c*6$xZ`E>T|JAcep)?ObiIG>LY&~`AA`N;K~t`i994lU>;GPeC#V=^}UhwV7h z-)WBM^(=zJ2P1q0mDlQue@G%U`jKkN1E*EGFg2g0e8n2as7r{+V~t^aZ~*U1^y)Vd z`P4w{hKVYDBQuwx?@m%azF>b_v{b<yX_sRRb0`C2K|g*Sl5<ObKR)EgLIaYYl}t(z zu^A__JlVsOYum)Oho~~l)2ke{%+Yfq<Ky4A%|>lYF6%UApN-mMm`&L(4teqGop@cR z6o5G_`Qwt`i-*j3Xs-a=_J^fboz!cT0tsm_5jpj2n|PKXK1&jtJl2*5LMJI@e_j!( zMUI+}(2Jt>e%xhEyR3=*c}5n-UBW148<)QfAAK=w`x|DPlJ$S;lKd@Fz#k2E;sahO zXq18zlIiZ($!Cas?jdq<Vy%J9vcx82!J6rn6f@^!?s3#ggjvZ@xh(y64dXLj5T;!9 zx1u)1Q~oj$uhc()4<s&}-;I+h0?gaYqDVdF=+zYco`z8a=ICuv+x*?Apvbl<mjeKK zF=x-YY@_fhk9~9$GL`xv9#F3t4<sVrTr&`xNn+hY?C@o&drl^oEm_Xes}O+OWSfdQ zrlX}XSr~I!71=(MvZiIo(XP0sdv!QO)e8W&NTyE~h)pl~G^5>S$#tGwXUWe!M2~@3 z;|X}($!MQsh@6Mm<I5gyiqu?$Ue1<ma`XmA&vP^|_?Ua$$NtPV>vGIs*72xSX_*D~ zAz7%nA-B};mrNf&BDQ!kn<1VwkWVJyE3yXbyNyFGtqG8dig0iVsEov%){G3$Ie;mp zVSWNCj?Orl)fD9`Z|8}u$}b5{)_E5fy=KJw+*0d=^lli=-Wk`}$7K7sEG)U|K~4%F zrgw9%Hi`^{dN)O1j1>FMU*U-@mfXr{w>;#o>WWy;Xg63gy9CL8*bohM;)6QLbn&$r z*#<iNg-cKXL(CeF+7-+WV2;cBrosh~E+}e}dN0B}*8q<TceJ2D@B>^_y;5tG{Nck6 zlSoZFg(=K7D+@339J6x$IK<Yu!qN{k44}6F0Hz96_QjFs`%VzKmQ;&nhmS_0`%I}h zg8uu=_)y~0d1w6$1Qu0wJK?H_>I3!W<gu?2ixFDMmTXK?3lZjCmR`x0sL(-pP6lMQ z2!&SM=O;dk6FGiuG8!^VAwT$+dK;v`UO^E0&;+jbf?q?ws)O~|(SRB13?FLoCxBa( z7VDBcyg@BY7Cv^WZ2)jR(C-(j*Sy3d50nL&Q;UOq<RNya!V$H_s#QB6K_04RTl}|V zVOj&>JI3X_Z$ks1R<hIzOXWm$ejH)uL~3c0N*@SKOlinnAP2Y#6URmm2ru}H0Q4?H z5z8Pq8>kz4Pa3nGGJ`hnfj2RAhFAyvg4Vob7G~%TOWK_{`IIHLlIpdB{%Sx-3oEYJ z0m)m?1Te=$)D8_HF01`jG$RDf5tZqNry5{YZOw2=y7a{;Ka~`QhmEmt0iLJcuRgY8 z>{b1x_D>@5FE;TVZx(`09sk1z|Nr>tWf8)_mxVB#h@mCSX!wfi8hs1yZ<V80u<<E1 zHec}SJAScsNIYHJ+A|P3UE3x6+f-#aG<A1}u2za-puMxUy0Y);<;sISmFls|m&gA5 zo+``X9!pgvU&&wT3bM5|7VGJncA>4UM(Aj-xhz!G@xIH|r|W#R)z)gOg|BPpeKppq ummjU@?&`TVaLs=uAa-1?fCwxVKEF`W)e{VK_4IYM_f@EQRCaf(IsOYC-Ww+X literal 0 HcmV?d00001 diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-tmop.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-tmop.ll index e918137bee27d..4b8615cc0ca00 100644 --- a/llvm/test/CodeGen/AArch64/sme2-intrinsics-tmop.ll +++ b/llvm/test/CodeGen/AArch64/sme2-intrinsics-tmop.ll @@ -119,7 +119,7 @@ define void @ftmopa_za16_f8(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <v ; CHECK-NEXT: mov z28.d, z3.d ; CHECK-NEXT: ftmopa za0.h, { z0.b, z1.b }, z2.b, z28[0] ; CHECK-NEXT: ret - call void @llvm.aarch64.sme.ftmopa.za16.nxv16i8(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk, i32 0) + call void @llvm.aarch64.sme.fp8.ftmopa.za16(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk, i32 0) ret void } @@ -129,7 +129,7 @@ define void @ftmopa_za32_f8(<vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <v ; CHECK-NEXT: mov z28.d, z3.d ; CHECK-NEXT: ftmopa za0.s, { z0.b, z1.b }, z2.b, z28[0] ; CHECK-NEXT: ret - call void @llvm.aarch64.sme.ftmopa.za32.nxv16i8(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk, i32 0) + call void @llvm.aarch64.sme.fp8.ftmopa.za32(i32 0, <vscale x 16 x i8> %zn1, <vscale x 16 x i8> %zn2, <vscale x 16 x i8> %zm, <vscale x 16 x i8> %zk, i32 0) ret void } _______________________________________________ cfe-commits mailing list [email protected] https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
