================
@@ -2541,6 +2542,66 @@ bool
AArch64InstructionSelector::earlySelect(MachineInstr &I) {
I.eraseFromParent();
return true;
}
+ case TargetOpcode::G_STORE: {
+ GStore &St = cast<GStore>(I);
+ auto MMO = St.getMMO();
+ LLT PtrTy = MRI.getType(St.getPointerReg());
+
+ // Only for handling atomic store with hint.
+ // Can only handle AddressSpace 0, 64-bit pointers.
+ if (!St.isAtomic() || PtrTy != LLT::pointer(0, 64)) {
+ return false;
+ }
+
+ AArch64AtomicStoreHint Hint = TII.decodeAtomicHintFlags(MMO.getFlags());
+ if (Hint == AArch64AtomicStoreHint::HINT_NONE)
+ return false;
+
+ unsigned HintOpc;
+ unsigned StoreSize = St.getMemSizeInBits().getValue();
+ Register ValueReg = St.getValueReg();
+ switch (StoreSize) {
+ case 8:
+ HintOpc = AArch64::ATOMIC_STORE_HINT_B;
+ break;
+ case 16: {
+ Register CastReg;
+ if (mi_match(ValueReg, MRI, m_GBitcast(m_Reg(CastReg)))) {
----------------
kmclaughlin-arm wrote:
The `AtomicExpandPass` converts floating-point atomic stores to integer stores
of the equivalent bitwidth (see
`AtomicExpandImpl::convertAtomicStoreToIntegerType`).
For 16-bit floating-point types, this produces an i16 value, e.g.
```
%1:fpr(bf16) = COPY $h0
%2:fpr(i16) = G_BITCAST %1:fpr(bf16)
G_STORE %2:fpr(i16), %0:gpr(p0) :: ("" store monotonic (i16) into %ir.ptr,
align 8)
```
SelectionDAG creates an `INSERT_SUBREG` during legalisation, but it has not
been created at this point for GlobalISel, which is why I am adding it here
before creating the pseudo.
https://github.com/llvm/llvm-project/pull/198316
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