github-actions[bot] wrote:

<!--LLVM CODE FORMAT COMMENT: {clang-format}-->


:warning: C/C++ code formatter, clang-format found issues in your code. 
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<details>
<summary>
You can test this locally with the following command:
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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- 
clang/lib/CodeGen/CGHLSLBuiltins.cpp clang/lib/CodeGen/CGHLSLRuntime.h 
clang/lib/Sema/HLSLBuiltinTypeDeclBuilder.cpp 
clang/lib/Sema/HLSLExternalSemaSource.cpp clang/lib/Sema/SemaHLSL.cpp 
llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp 
llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp --diff_from_common_commit
``````````

:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:

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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp 
b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index 3d0d2cd30..f68721fd1 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -178,7 +178,7 @@ private:
                        unsigned NewOpcode, unsigned NegateOpcode = 0) const;
 
   bool selectInterlockedOp(Register ResVReg, SPIRVTypeInst ResType,
-                            MachineInstr &I, unsigned Opcode) const;
+                           MachineInstr &I, unsigned Opcode) const;
 
   bool selectAtomicCmpXchg(Register ResVReg, SPIRVTypeInst ResType,
                            MachineInstr &I) const;
@@ -2446,9 +2446,9 @@ bool SPIRVInstructionSelector::selectAtomicRMW(Register 
ResVReg,
 }
 
 bool SPIRVInstructionSelector::selectInterlockedOp(Register ResVReg,
-                                                    SPIRVTypeInst ResType,
-                                                    MachineInstr &I,
-                                                    unsigned Opcode) const {
+                                                   SPIRVTypeInst ResType,
+                                                   MachineInstr &I,
+                                                   unsigned Opcode) const {
   Register Ptr = I.getOperand(2).getReg();
   Register Value = I.getOperand(3).getReg();
 

``````````

</details>


https://github.com/llvm/llvm-project/pull/180804
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