llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: SiHuaN (sihuan)
<details>
<summary>Changes</summary>
Add the __riscv_{pas,psa,psas,pssa,paas,pasa}_x_* header wrappers over new
__builtin_riscv_* builtins.
---
Patch is 32.52 KiB, truncated to 20.00 KiB below, full version:
https://github.com/llvm/llvm-project/pull/205251.diff
5 Files Affected:
- (modified) clang/include/clang/Basic/BuiltinsRISCV.td (+22)
- (modified) clang/lib/CodeGen/TargetBuiltins/RISCV.cpp (+49)
- (modified) clang/lib/Headers/riscv_packed_simd.h (+22)
- (modified) clang/test/CodeGen/RISCV/rvp-intrinsics.c (+398)
- (modified) cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
(+126)
``````````diff
diff --git a/clang/include/clang/Basic/BuiltinsRISCV.td
b/clang/include/clang/Basic/BuiltinsRISCV.td
index 3a1b54763bae6..ee20fefadd7c3 100644
--- a/clang/include/clang/Basic/BuiltinsRISCV.td
+++ b/clang/include/clang/Basic/BuiltinsRISCV.td
@@ -181,6 +181,28 @@ def pasubu_u8x8 : RISCVBuiltin<"_Vector<8, unsigned
char>(_Vector<8, unsigned ch
def pasubu_u16x4 : RISCVBuiltin<"_Vector<4, unsigned short>(_Vector<4,
unsigned short>, _Vector<4, unsigned short>)">;
def pasubu_u32x2 : RISCVBuiltin<"_Vector<2, unsigned int>(_Vector<2, unsigned
int>, _Vector<2, unsigned int>)">;
+// Packed Exchanged Addition and Subtraction (32-bit)
+def pas_x_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>,
_Vector<2, short>)">;
+def psa_x_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>,
_Vector<2, short>)">;
+def psas_x_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>,
_Vector<2, short>)">;
+def pssa_x_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>,
_Vector<2, short>)">;
+def paas_x_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>,
_Vector<2, short>)">;
+def pasa_x_i16x2 : RISCVBuiltin<"_Vector<2, short>(_Vector<2, short>,
_Vector<2, short>)">;
+
+// Packed Exchanged Addition and Subtraction (64-bit)
+def pas_x_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>,
_Vector<4, short>)">;
+def pas_x_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2,
int>)">;
+def psa_x_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>,
_Vector<4, short>)">;
+def psa_x_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2,
int>)">;
+def psas_x_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>,
_Vector<4, short>)">;
+def psas_x_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2,
int>)">;
+def pssa_x_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>,
_Vector<4, short>)">;
+def pssa_x_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2,
int>)">;
+def paas_x_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>,
_Vector<4, short>)">;
+def paas_x_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2,
int>)">;
+def pasa_x_i16x4 : RISCVBuiltin<"_Vector<4, short>(_Vector<4, short>,
_Vector<4, short>)">;
+def pasa_x_i32x2 : RISCVBuiltin<"_Vector<2, int>(_Vector<2, int>, _Vector<2,
int>)">;
+
// Packed Absolute Value and Absolute Difference (32-bit)
def pabd_i8x4 : RISCVBuiltin<"_Vector<4, unsigned char>(_Vector<4, signed
char>, _Vector<4, signed char>)">;
def pabd_i16x2 : RISCVBuiltin<"_Vector<2, unsigned short>(_Vector<2, short>,
_Vector<2, short>)">;
diff --git a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
index a1e9acb7ec2c8..d5b027fe5f8fe 100644
--- a/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/RISCV.cpp
@@ -1220,6 +1220,25 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned
BuiltinID,
case RISCV::BI__builtin_riscv_pasubu_u8x8:
case RISCV::BI__builtin_riscv_pasubu_u16x4:
case RISCV::BI__builtin_riscv_pasubu_u32x2:
+ // Packed Exchanged Addition and Subtraction
+ case RISCV::BI__builtin_riscv_pas_x_i16x2:
+ case RISCV::BI__builtin_riscv_pas_x_i16x4:
+ case RISCV::BI__builtin_riscv_pas_x_i32x2:
+ case RISCV::BI__builtin_riscv_psa_x_i16x2:
+ case RISCV::BI__builtin_riscv_psa_x_i16x4:
+ case RISCV::BI__builtin_riscv_psa_x_i32x2:
+ case RISCV::BI__builtin_riscv_psas_x_i16x2:
+ case RISCV::BI__builtin_riscv_psas_x_i16x4:
+ case RISCV::BI__builtin_riscv_psas_x_i32x2:
+ case RISCV::BI__builtin_riscv_pssa_x_i16x2:
+ case RISCV::BI__builtin_riscv_pssa_x_i16x4:
+ case RISCV::BI__builtin_riscv_pssa_x_i32x2:
+ case RISCV::BI__builtin_riscv_paas_x_i16x2:
+ case RISCV::BI__builtin_riscv_paas_x_i16x4:
+ case RISCV::BI__builtin_riscv_paas_x_i32x2:
+ case RISCV::BI__builtin_riscv_pasa_x_i16x2:
+ case RISCV::BI__builtin_riscv_pasa_x_i16x4:
+ case RISCV::BI__builtin_riscv_pasa_x_i32x2:
// Packed Absolute Value and Absolute Difference
case RISCV::BI__builtin_riscv_pabd_i8x4:
case RISCV::BI__builtin_riscv_pabd_i16x2:
@@ -1260,6 +1279,36 @@ Value *CodeGenFunction::EmitRISCVBuiltinExpr(unsigned
BuiltinID,
case RISCV::BI__builtin_riscv_pasubu_u32x2:
ID = Intrinsic::riscv_pasubu;
break;
+ case RISCV::BI__builtin_riscv_pas_x_i16x2:
+ case RISCV::BI__builtin_riscv_pas_x_i16x4:
+ case RISCV::BI__builtin_riscv_pas_x_i32x2:
+ ID = Intrinsic::riscv_pas;
+ break;
+ case RISCV::BI__builtin_riscv_psa_x_i16x2:
+ case RISCV::BI__builtin_riscv_psa_x_i16x4:
+ case RISCV::BI__builtin_riscv_psa_x_i32x2:
+ ID = Intrinsic::riscv_psa;
+ break;
+ case RISCV::BI__builtin_riscv_psas_x_i16x2:
+ case RISCV::BI__builtin_riscv_psas_x_i16x4:
+ case RISCV::BI__builtin_riscv_psas_x_i32x2:
+ ID = Intrinsic::riscv_psas;
+ break;
+ case RISCV::BI__builtin_riscv_pssa_x_i16x2:
+ case RISCV::BI__builtin_riscv_pssa_x_i16x4:
+ case RISCV::BI__builtin_riscv_pssa_x_i32x2:
+ ID = Intrinsic::riscv_pssa;
+ break;
+ case RISCV::BI__builtin_riscv_paas_x_i16x2:
+ case RISCV::BI__builtin_riscv_paas_x_i16x4:
+ case RISCV::BI__builtin_riscv_paas_x_i32x2:
+ ID = Intrinsic::riscv_paas;
+ break;
+ case RISCV::BI__builtin_riscv_pasa_x_i16x2:
+ case RISCV::BI__builtin_riscv_pasa_x_i16x4:
+ case RISCV::BI__builtin_riscv_pasa_x_i32x2:
+ ID = Intrinsic::riscv_pasa;
+ break;
case RISCV::BI__builtin_riscv_pabd_i8x4:
case RISCV::BI__builtin_riscv_pabd_i16x2:
case RISCV::BI__builtin_riscv_pabd_i8x8:
diff --git a/clang/lib/Headers/riscv_packed_simd.h
b/clang/lib/Headers/riscv_packed_simd.h
index 56f6b108d5f14..5aa00f1519671 100644
--- a/clang/lib/Headers/riscv_packed_simd.h
+++ b/clang/lib/Headers/riscv_packed_simd.h
@@ -206,6 +206,28 @@ __packed_sh1add(psh1add_u32x2, uint32x2_t)
__packed_sh1sadd(pssh1sadd_i16x4, int16x4_t)
__packed_sh1sadd(pssh1sadd_i32x2, int32x2_t)
+/* Packed Exchanged Addition and Subtraction (32-bit) */
+__packed_binary_builtin(pas_x_i16x2, int16x2_t, __builtin_riscv_pas_x_i16x2)
+__packed_binary_builtin(psa_x_i16x2, int16x2_t, __builtin_riscv_psa_x_i16x2)
+__packed_binary_builtin(psas_x_i16x2, int16x2_t, __builtin_riscv_psas_x_i16x2)
+__packed_binary_builtin(pssa_x_i16x2, int16x2_t, __builtin_riscv_pssa_x_i16x2)
+__packed_binary_builtin(paas_x_i16x2, int16x2_t, __builtin_riscv_paas_x_i16x2)
+__packed_binary_builtin(pasa_x_i16x2, int16x2_t, __builtin_riscv_pasa_x_i16x2)
+
+/* Packed Exchanged Addition and Subtraction (64-bit) */
+__packed_binary_builtin(pas_x_i16x4, int16x4_t, __builtin_riscv_pas_x_i16x4)
+__packed_binary_builtin(psa_x_i16x4, int16x4_t, __builtin_riscv_psa_x_i16x4)
+__packed_binary_builtin(psas_x_i16x4, int16x4_t, __builtin_riscv_psas_x_i16x4)
+__packed_binary_builtin(pssa_x_i16x4, int16x4_t, __builtin_riscv_pssa_x_i16x4)
+__packed_binary_builtin(paas_x_i16x4, int16x4_t, __builtin_riscv_paas_x_i16x4)
+__packed_binary_builtin(pasa_x_i16x4, int16x4_t, __builtin_riscv_pasa_x_i16x4)
+__packed_binary_builtin(pas_x_i32x2, int32x2_t, __builtin_riscv_pas_x_i32x2)
+__packed_binary_builtin(psa_x_i32x2, int32x2_t, __builtin_riscv_psa_x_i32x2)
+__packed_binary_builtin(psas_x_i32x2, int32x2_t, __builtin_riscv_psas_x_i32x2)
+__packed_binary_builtin(pssa_x_i32x2, int32x2_t, __builtin_riscv_pssa_x_i32x2)
+__packed_binary_builtin(paas_x_i32x2, int32x2_t, __builtin_riscv_paas_x_i32x2)
+__packed_binary_builtin(pasa_x_i32x2, int32x2_t, __builtin_riscv_pasa_x_i32x2)
+
/* Packed Minimum and Maximum (32-bit) */
__packed_binary_builtin(pmin_i8x4, int8x4_t, __builtin_elementwise_min)
__packed_binary_builtin(pmin_i16x2, int16x2_t, __builtin_elementwise_min)
diff --git a/clang/test/CodeGen/RISCV/rvp-intrinsics.c
b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
index cc388d0ab0328..d3f153109b904 100644
--- a/clang/test/CodeGen/RISCV/rvp-intrinsics.c
+++ b/clang/test/CodeGen/RISCV/rvp-intrinsics.c
@@ -1664,6 +1664,404 @@ int32x2_t test_pssh1sadd_i32x2(int32x2_t a, int32x2_t
b) {
return __riscv_pssh1sadd_i32x2(a, b);
}
+/* Packed Exchanged Addition and Subtraction (32-bit) */
+// RV32-LABEL: define dso_local i32 @test_pas_x_i16x2(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pas.v2i16(<2 x i16>
[[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_pas_x_i16x2(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pas.v2i16(<2 x i16>
[[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+int16x2_t test_pas_x_i16x2(int16x2_t a, int16x2_t b) {
+ return __riscv_pas_x_i16x2(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_psa_x_i16x2(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.psa.v2i16(<2 x i16>
[[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_psa_x_i16x2(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.psa.v2i16(<2 x i16>
[[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+int16x2_t test_psa_x_i16x2(int16x2_t a, int16x2_t b) {
+ return __riscv_psa_x_i16x2(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_psas_x_i16x2(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.psas.v2i16(<2 x
i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_psas_x_i16x2(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.psas.v2i16(<2 x
i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+int16x2_t test_psas_x_i16x2(int16x2_t a, int16x2_t b) {
+ return __riscv_psas_x_i16x2(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pssa_x_i16x2(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pssa.v2i16(<2 x
i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_pssa_x_i16x2(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pssa.v2i16(<2 x
i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+int16x2_t test_pssa_x_i16x2(int16x2_t a, int16x2_t b) {
+ return __riscv_pssa_x_i16x2(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_paas_x_i16x2(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paas.v2i16(<2 x
i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_paas_x_i16x2(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.paas.v2i16(<2 x
i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+int16x2_t test_paas_x_i16x2(int16x2_t a, int16x2_t b) {
+ return __riscv_paas_x_i16x2(a, b);
+}
+
+// RV32-LABEL: define dso_local i32 @test_pasa_x_i16x2(
+// RV32-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasa.v2i16(<2 x
i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV32-NEXT: ret i32 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i32 @test_pasa_x_i16x2(
+// RV64-SAME: i32 noundef [[A_COERCE:%.*]], i32 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i32 [[A_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i32 [[B_COERCE]] to <2 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <2 x i16> @llvm.riscv.pasa.v2i16(<2 x
i16> [[TMP0]], <2 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <2 x i16> [[TMP2]] to i32
+// RV64-NEXT: ret i32 [[TMP3]]
+//
+int16x2_t test_pasa_x_i16x2(int16x2_t a, int16x2_t b) {
+ return __riscv_pasa_x_i16x2(a, b);
+}
+
+/* Packed Exchanged Addition and Subtraction (64-bit) */
+// RV32-LABEL: define dso_local i64 @test_pas_x_i16x4(
+// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pas.v4i16(<4 x i16>
[[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pas_x_i16x4(
+// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pas.v4i16(<4 x i16>
[[TMP0]], <4 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int16x4_t test_pas_x_i16x4(int16x4_t a, int16x4_t b) {
+ return __riscv_pas_x_i16x4(a, b);
+}
+
+// RV32-LABEL: define dso_local i64 @test_psa_x_i16x4(
+// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.psa.v4i16(<4 x i16>
[[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_psa_x_i16x4(
+// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.psa.v4i16(<4 x i16>
[[TMP0]], <4 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int16x4_t test_psa_x_i16x4(int16x4_t a, int16x4_t b) {
+ return __riscv_psa_x_i16x4(a, b);
+}
+
+// RV32-LABEL: define dso_local i64 @test_psas_x_i16x4(
+// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.psas.v4i16(<4 x
i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_psas_x_i16x4(
+// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.psas.v4i16(<4 x
i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int16x4_t test_psas_x_i16x4(int16x4_t a, int16x4_t b) {
+ return __riscv_psas_x_i16x4(a, b);
+}
+
+// RV32-LABEL: define dso_local i64 @test_pssa_x_i16x4(
+// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pssa.v4i16(<4 x
i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_pssa_x_i16x4(
+// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV64-NEXT: [[ENTRY:.*:]]
+// RV64-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// RV64-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.pssa.v4i16(<4 x
i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV64-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV64-NEXT: ret i64 [[TMP3]]
+//
+int16x4_t test_pssa_x_i16x4(int16x4_t a, int16x4_t b) {
+ return __riscv_pssa_x_i16x4(a, b);
+}
+
+// RV32-LABEL: define dso_local i64 @test_paas_x_i16x4(
+// RV32-SAME: i64 noundef [[A_COERCE:%.*]], i64 noundef [[B_COERCE:%.*]])
#[[ATTR0]] {
+// RV32-NEXT: [[ENTRY:.*:]]
+// RV32-NEXT: [[TMP0:%.*]] = bitcast i64 [[A_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP1:%.*]] = bitcast i64 [[B_COERCE]] to <4 x i16>
+// RV32-NEXT: [[TMP2:%.*]] = call <4 x i16> @llvm.riscv.paas.v4i16(<4 x
i16> [[TMP0]], <4 x i16> [[TMP1]])
+// RV32-NEXT: [[TMP3:%.*]] = bitcast <4 x i16> [[TMP2]] to i64
+// RV32-NEXT: ret i64 [[TMP3]]
+//
+// RV64-LABEL: define dso_local i64 @test_paas_x_i16x4(
+// RV64-SAME: i64 noundef [[A_COERCE:%.*]], i...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/205251
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